Fast access to buffer circuits

Details Fast access to buffer circuits Fast access to buffer circuits

1999-06-02

2002-08-13

Kim, Matthew (Department: 2186)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S053000, C711S154000, C365S189050, C365S189080

Reexamination Certificate

active

06434655

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a buffer circuit and, more particularly, to a buffer circuit of an external memory interface of a microprocessor, with fast access to data elements contained in the buffer circuit.
BACKGROUND OF THE INVENTION
The external memory interface of a complex circuit such as a microprocessor has to manage communication with the microprocessor in both directions; i.e., from the microprocessor to the external memory interface and from the external memory interface to the microprocessor. The communication is carried out in the form of information element exchanges, usually by a wired link called a two-way transmission bus. The information elements may be memory addresses, data elements or control instructions.
The information elements are in the form of binary data elements which constitute words. The information elements flow from the microprocessor to the external memory interface when requests for access to the external memory are sent by the microprocessor. The information elements flow from the external memory interface to the microprocessor when the appropriate responses to these requests are sent back. In both cases, the information elements flow via the transmission bus.
The external memory interface must therefore have two buffer circuits available: an input buffer circuit and an output buffer circuit. The requests for access to the external memory sent by the microprocessor are stored in the input buffer circuit of the external memory interface. These requests are then decoded by the external memory interface. Through this decoding, the memory addresses to be accessed as well as the required type of access are obtained. This go required type of access may be a write mode access or a read mode access. It is only then that the real access to the external memory is effective. When reading the external memory, a word that is read is stored in the output buffer circuit of the external memory interface. It is then sent to the microprocessor via the transmission bus.
This transfer of information may be disturbed for various reasons. The rate of information transfer is set by a clock. The transfer may be totally blocked for several clock cycles. Now the external memory interface cannot meet the requests for access to the external memory if a previous access to this external memory has not yet been processed. Furthermore, a response to a request for access to the external memory cannot be sent by the transmission bus if another exchange of information has taken place at the same time on this transmission bus. These possible disturbances in information exchanges necessitate an internal memory in the input and output buffer circuits of the external memory interface.
The following description shall refer solely to the input buffer circuit of an external memory interface both in the explanation of the prior art and in the context of the presentation of the invention in itself. However, it will be clear that the buffer circuit according to the invention may be applied to any other interface whose performance characteristics can be improved by the circuit according to the invention.
FIG. 1
is a block diagram of the conventional and essential elements involved during the information exchanges between a complex circuit, such as a microprocessor, and an external memory interface. A microprocessor
1
is connected to an external memory interface
2
via a transmission bus
22
. This transmission bus
22
conveys the data to a buffer circuit
3
of the external memory interface
2
. This buffer circuit
3
includes an input buffer circuit
4
and an output buffer circuit
5
. The input buffer circuit
4
receives the access request from the microprocessor
1
. The output buffer circuit
5
sends the responses to these requests after completion of a processing operation. A memory space
7
of an external memory
8
, which is the object of the request, may be read, written in or erased through the memory access
6
.
FIG. 2
shows a prior art input buffer circuit of an external memory interface. This input buffer circuit
20
may be the type of input buffer circuit
4
contained in the external memory interface described in FIG.
1
. The input buffer circuit
20
receives the transmission bus
22
at an input
21
. The requests for access to the external memory that are conveyed by the transmission bus
22
are received by a bus interface
23
. This bus interface
23
, of a register type, outputs an INW signal. A link
24
connects the bus interface
23
and a first input E
1
of a first multiplexer
25
. A link
27
connects a connection point
26
of the link
24
and a RAM memory
28
. A link
29
connects the RAM memory
28
and a second input E
2
of the first multiplexer
25
. A link
211
connects an output S
1
of the first multiplexer
25
and an input E
3
of a register
212
. At an output S
2
, the register
212
provides an output signal OUTW to a decoding interface
213
of the external memory interface.
The description of the operation of the circuit shown in
FIG. 2
follows. The requests for access to the external memory are received by the bus interface
23
. If all the previous requests have been processed, the RAM memory
28
is empty and is not active. The last request sent by the microprocessor is directly transmitted to the first register
212
through the first input E
1
of the first multiplexer
25
and the links
24
and
211
in the form of the signal INW. This request may then be directly exploited by the decoding interface
213
.
If one or more requests have not yet been processed at the time of the reception of a new request by the bus interface
23
, then the RAM memory
28
is not empty. In this case, and also when the data transfer is blocked, the request or requests that reach the input buffer circuit are written in the RAM memory
28
. When a request is read in the RAM memory
28
, it is transmitted to the first register
212
via the second input E
2
of the first multiplexer
25
and the links
29
and
211
. The RAM memory
28
used in this type of buffer circuit does not provide the capability to read a data element during a clock period when this data element is written (this characteristic is known as a “no read through capability”).
The rates of the transmissions between the complex circuit or microprocessor and the external memory interface are set by a clock. When a data element is written in a specific memory space of the RAM memory
28
during a specified clock period, this very same memory space of the RAM memory
28
is accessible in read mode at the next clock cycle only. Consequently, the data element is transmitted to the first register
212
only two clock periods after the clock period corresponding to the writing of the data element in the RAM type memory
28
. There is thus a loss of time in the transmission of data elements between the bus interface
23
and the decoding interface
213
. Indeed, a period of time equal to the duration of a clock period is lost. We will now refer to the existence of a latency cycle.
FIG. 3
shows a timing diagram with four timing lines
31
-
34
. The first timing line
31
shows the clock signal. The second timing line
32
shows the write access to the RAM memory
28
. The third timing line
33
shows the read access to the RAM memory
28
. The fourth timing line
34
shows the state of the first register
212
. For this timing diagram, the X-axis indicates the passage of time. It is subdivided into four equal time intervals. Each of the four time intervals corresponds to a clock period.
A memory space of the RAM memory
28
is written in during the first clock period. This write access is represented in the second timing line
32
by a high level pulse. During this first clock period, this memory space of the RAM memory
28
changes its value and cannot be read. This new and correct value is available at the same memory space of the RAM memory
28
during the second clock period. This possible read access is represented in the third timing line
33
by a high lev

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