Fast access memory array

Details Fast access memory array Fast access memory array

1995-07-07

1997-10-07

Dinh, Son T.

Static information storage and retrieval

Interconnection arrangements

365149, 36518909, 365203, G11C 506

Patent

active

056755295

ABSTRACT:
A memory array with improved access time is disclosed. In one embodiment, the memory array includes a plurality of memory cells arranged in rows and columns. Each one of the plurality of columns includes a global bit line, a local bit line with a memory cell coupled thereto, and an MOS switch configured to selectively couple the local bit line and the global bit line in response to a column select signal. In a second embodiment, the memory array includes a plurality of sense amplifiers located at the periphery of the array, and a plurality of columns associated with the plurality of sense amplifiers respectively. Each one of the plurality of columns includes a global bit line, a local bit line with a memory cell coupled thereto; and a switch coupled between the local bit line and the global bit line and configured to selectively move the global bit line in response to the contents of the memory cell during a read operation. In either embodiment, the switch is an MOS transistor having its drain coupled to the global bit line, its gate coupled to the local bit line, and its source coupled to a reference voltage. During operation, a word line coupled to the memory cell is activated at approximately the same time as the column select signal to access the memory cell. The configuration of the MOS transistor switches provides for maximum transconductance in discharging the global bit lines.

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"A IMb CMOS DRAM with a Divided Bitline Matrix Architecture", by Taylor & Johnson, Mostek Corporation, ISSCC 85, Feb. 15, 1985, pp. 242-243.

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