Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2006-03-21
2006-03-21
Perveen, Rehana (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S035000, C710S058000, C710S060000, C710S061000
Reexamination Certificate
active
07016989
ABSTRACT:
A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.
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Intel Corporation
Perveen Rehana
Shah Ami P.
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