Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-12
2010-12-14
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07853914
ABSTRACT:
A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout signal can be replicated, wherein each window is associated with a source of the high fanout signal. For each source of the high fanout signal, the source can be connected to load pins of the window associated with the source and the source can be placed within the window associated with the source. The placed circuit design can be output.
REFERENCES:
patent: 6205572 (2001-03-01), Dupenloup
patent: 7222318 (2007-05-01), Srinivasan
Xilinx, Inc.; U.S. Appl. No. 11/361,369; by Singh et al.; filed Feb. 24, 2006.
Xilinx, Inc.; U.S. Appl. No. 11/361,370; by Singh et al.; filed Feb. 24, 2006.
Rajeev Murgai; “On the Global Fanout Optimization Problem”; Copyright 1999 IEEE; ICCAD:1999; pp. 511-515.
Kanwar Jit Sing. et al.; “A Heuristic Algorithm for the Fanout Problem”; Copyright 1990 IEEE; 17th ACM/IEEE Design Automation Conference; pp. 357-360.
Chaudhary Kamal
Payette Benoit
Singh Amit
Srinivasan Sankaranarayanan
Cuenot Kevin T.
Do Thuan
Maunu LeRoy D.
Xilinx , Inc.
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