Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-15
2004-05-11
Whitmore, Satcy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06735751
ABSTRACT:
FIELD OF THE INVENTION
1. Field of the Invention
The present invention relates to a false path detecting apparatus and a false path detecting method for detecting a false path implying a path that is not active in a combination of circuit operations, in circuits generated by behavioral synthesis, and a program for the same.
2. Description of the Related Art
Conventionally, as a technique used to design a large logical circuit, there is a behavioral synthesizing technique of automatically generating an RTL (Register Transfer Level) circuit, on the basis of a behavior description describing only a behavior, which does not contain a structure of hard-ware. Moreover, there is a logically synthesizing technique of converting this RTL circuit into a net list of a gate level. As for the circuit generated at this time, the circuit is generated under a predetermined delay constraint so that the delays of all paths (routes of data) are in a range of a predetermined period. At this time, in particular, in a circuit having a state transition and the like, there is a combination path of nets that do not become active at the same time throughout all the states. This path is a false path. The final false path is determined by the combination of paths that become active in each other states (hereafter, referred to as a true path).
If the logically synthesizing circuit satisfies only the delay constraint of the true path, the circuit is normally operated even if the delay of the false path is at the longest. So, the information with regard to the true path and the false path is reflected in the logical synthesis, and the delay constraint is not performed on the false path. At this time, as a method of extracting the information with regard to the true path and the false path from the circuit information after the behavioral synthesis, there is a method of checking the true path or the false path by referring to the information of the true path and comparing it, for the patterns of all the paths of the circuit. The false path detecting apparatus using the method will be described below with reference to the drawings.
FIG. 1
is a view showing a conventional false path detecting apparatus. A false path detecting apparatus
3
receives a circuit information outputted by a behavioral synthesizing system
1
, a data flow information and a resource assignment information through a memory
4
, and carries out a process as described below, and then outputs a false path information.
A true path lister
31
extracts all the true paths in the circuit from the circuit information, the data flow information and the resource assignment information, and stores them in a true path memory
34
. For all partial circuits shared by an operating unit in partial circuits constituted by any combination in the true path memory
34
, a false path candidate generator
32
extracts all paths existing in the partial circuit except the true path constituting the partial circuit, and outputs them to a false path minimizing device
33
. The false path minimizing device
33
shortens the path from both the ends thereof while checking that the false path candidate is not the true path, for all the false path candidates. Then, it outputs the shortest false path, which does not contain a redundant path, to an output device
2
.
As mentioned above, conventionally, the information with regard to all the true paths is stored, which results in a problem that a large number of memories are required in a case of a circuit information of a large integrated circuit. Also, in order to attain the minimization of the false path candidate, the comparison with the true path is repeated, which results in a problem that it takes a long time to complete the process. Also, it is sure that the size of an integrated circuit is further increased in future. Depending on a case, this results in a problem that it can not be applied to a further large circuit because of the lack of memories, the process time which can not be within a process time durable for practical use and other reasons.
SUMMARY OF THE INVENTION
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a false path detecting apparatus and a false path detecting method in which a usage amount of memories is smaller and a process is carried out at a higher speed, and that program.
In order to achieve an aspect of the present invention, a false path detecting method, includes: (a) providing a data flow occurrence condition that a net becomes active, with regard to each of a plurality of nets; (b) selecting one of the plurality of nets as a selected net; (c) selecting, as a first specific net, a net connected to an input side or an output side of an element connected to an input side or an output side of the selected net of the plurality of nets; (d) adding the first specific net to the selected net to generate a first specific path; and (e) judging whether or not the first specific path is a false path based on the data flow occurrence condition of the selected net and the data flow occurrence condition of the first specific net.
In this case, the false path detecting method further includes: (f) selecting, as a second specific net, a net connected to an input side or an output side of an element connected to an input side or an output side of the first specific path of the plurality of nets, when in the (e) the first specific path is not a false path; (g) adding the second specific net to the first specific path to generate a second specific path; and (h) judging whether or not the second specific path is a false path based on the data flow occurrence condition of the first specific path and the data flow occurrence condition of the second specific net.
Also in this case, a circuit including the false path can be designed without consideration of a delay time of the false path.
Further in this case, the data flow occurrence condition is represented as an identifier or an OR operation of identifiers.
In this case, whether or not the first specific path is the false path depends on a comparison of the identifier of the data flow occurrence condition of the selected net to the identifier of the data flow occurrence condition of the first specific net.
Also in this case, the first specific path is the false path when a result of an AND operation between the identifier of the data flow occurrence condition of the selected net and the identifier of the data flow occurrence condition of the first specific net corresponds to “0”.
Further in this case, when the element connected to the input side or the output side of the selected net is an input terminal, an output terminal or a memory element, the (c), (d) and (e) are not performed.
In this case, the data flow occurrence condition is provided by an behavioral synthesis of automatically generating an RTL (Register Transfer Level) circuit based on a behavior description describing only a behavior, which does not contain a structure of hard-ware.
Also in this case, the false path detecting method is performed when the behavioral synthesis is performed.
Further in this case, the false path detecting method further includes: (i) judging whether or not the false path includes a redundant net; and (j) outputting the false path other than the false path including the redundant net.
In this case, the data flow occurrence condition is represented as an identifier or an OR operation of identifiers, and in the (i), when an AND operation with regard to the plurality of identifiers of the plurality of nets of the false path in order of an input side or an output side of the false path is performed until a result of the AND operation corresponds to “0” and the net on which the AND operation is not yet performed remains in case of the result corresponding to the “0”, the false path is judged to include the redundant net of the remaining net.
In order to achieve another aspect of the present invention, a false path detecting apparatus, includes: an active condition extracting
NEC Electronics Corporation
Scully Scott Murphy & Presser
Whitmore Satcy A.
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