Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2011-08-02
2011-08-02
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S502000, C375S238000
Reexamination Certificate
active
07992030
ABSTRACT:
Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
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McKinnon, J.D.; Active Circuit for Neutralizing Capacitive Loading; Technical Disclosure Bulletin 11-75, p. 1933-1934; Nov. 1975.
McMillan Henry G.
Patel Pravin
Purrington Challis L.
Tobin Gwendolyn R.
West Christopher C.
Abbaszadeh Jaweed A
Carey, Rodriquez, Greenberg & Paul
Greenberg, Esq. Steven M.
International Business Machines - Corporation
Lee Thomas
LandOfFree
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