Failure tolerant memory device, in particular of the flash EEPRO

Details Failure tolerant memory device, in particular of the flash EEPRO Failure tolerant memory device, in particular of the flash EEPRO

1995-05-31

1997-10-28

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518522, 36518907, 365200, 365210, G11C 1134

Patent

active

056823495

ABSTRACT:
Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

REFERENCES:
patent: 4733394 (1988-03-01), Giebel
patent: 4779272 (1988-10-01), Kohda et al.
patent: 5355339 (1994-10-01), Oh et al.
patent: 5426608 (1995-06-01), Higashitani

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