Failure test method for split gate flash memory

Details Failure test method for split gate flash memory Failure test method for split gate flash memory

2006-05-23

2006-05-23

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S185090, C365S185280, C365S185290, C365S185330

Reexamination Certificate

active

07050344

ABSTRACT:
A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.

REFERENCES:
patent: 5659550 (1997-08-01), Mehrotra et al.
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6515923 (2003-02-01), Cleeves
patent: 6567305 (2003-05-01), Nakamura
patent: 6584018 (2003-06-01), Tuan et al.

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