Failure self-diagnosis device for semiconductor memory

Details Failure self-diagnosis device for semiconductor memory Failure self-diagnosis device for semiconductor memory

1998-09-17

1999-12-28

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36518907, 371 225, 371 251, G11C 700

Patent

active

060090286

ABSTRACT:
The failure self-diagnosis device for semiconductor memory, comprises: a CPU for controlling a diagnosis operation; a data generating circuit for generating a test data to be written into memory elements to be diagnosed and an expected data which is the same as a data to be precisely read out from the memory elements after the test data was precisely written into the memory elements; a clock generating circuit for outputting a clock signal; address generating circuits, each of which is arranged with each of the memory elements to be diagnosed, for generating address assigning signals by synchronizing with the clock signal; comparators, each of which is arranged with each of the memory elements to be diagnosed, for comparing read out data which was read out from each of the memory elements by synchronizing with the address assigning signal, with the expected data; and diagnosis stop circuits, each of which is arranged with each of the memory elements to be diagnosed, for stopping the diagnosis operation of each of the memory elements when a corresponding comparator judges that the read out data from a corresponding memory element is not coincident with the expected data.

REFERENCES:
patent: 5271015 (1993-12-01), Akiyama
patent: 5856985 (1999-01-01), Fujisaki
patent: 5859804 (1999-01-01), Hedberg et al.
patent: 5862151 (1999-01-01), Fagerness
patent: 5864565 (1999-01-01), Ochoa et al.

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