Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-02
2004-08-03
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06772402
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of and apparatus for grouping failure paths of integrated circuit designs, and to a computer-readable medium for enabling a computer to perform such grouping.
BACKGROUND ART
Very large scale integrated (VLSI) circuit design is a complex and time consuming engineering task. Functional blocks are groupings of integrated circuits to be fabricated, e.g., adders, shifters, and clock distribution mechanisms. Before an integrated circuit can be fabricated, the integrated circuit must pass many correctness, i.e., verification, checks if the circuit has many functional blocks. One such verification check is a static timing analysis. A static timing analysis traces all signal paths through a circuit and verifies that all signal paths meet or exceed the required timing constraints, i.e., the circuit is able to operate at or above a specified frequency. Passing paths are signal paths meeting or exceeding the timing constraints and failing paths are signal paths not meeting the timing constraints.
FIG. 1
is a portion of an exemplary circuit design, generally indicated by reference numeral
100
. Circuit design portion
100
includes a set of functional blocks, i.e., FB
1
, FB
2
, FB
1
A, FB
2
A, and FB
3
-FB
16
referenced by numerals
102
-
119
respectively, connected via signal paths. Functional blocks
104
,
110
, and
116
represent functional blocks receiving a signal from another portion (not shown) of the circuit design or from an input port of the circuit design. Functional blocks
104
,
110
, and
116
derive a signal using signal paths to connected functional blocks
102
and
105
,
108
and
111
,
114
and
117
, respectively.
Functional blocks
102
-
119
represent processing circuits, i.e., a set of one or more transistors, for processing the input signal received from other functional blocks of the circuit design (not shown) or from an input port (not shown) of the circuit design. Functional blocks
102
-
119
may be any of a wide range of processing functionality, e.g., a single transistor, an inverter, an arithmetic logic unit (ALU), a floating point unit (FPU), or any other logic processing unit. Functional blocks
102
-
119
process the received input signal and transmit a signal to either (1) another of the functional blocks
105
-
116
or (2) an output port (not shown) of the circuit design.
Typically in a timing analysis resulting from a computer simulation of a proposed circuit design, transistors comprising the integrated circuit are grouped into functional blocks, and a graph of connected functional blocks, e.g., the graph of portion
100
of
FIG. 1
, is constructed. Each functional block may contain one or more transistors or functional blocks.
The timing analysis converts the functional block graph (
FIG. 1
) to a path and node graph (
FIG. 2
) by converting the signal path connecting functional blocks into nodes and converting the functional blocks into connections between nodes. In other words, the nodes are extracted from the functional block graph signal paths and logically connected by paths based on the functional blocks. Thus, the signal path connecting FB
1
to FB
2
is converted to a node generally indicated by a dashed line object
120
in FIG.
1
. The signal path connecting FB
3
to FB
1
and FB
1
A is converted to a node generally indicated by a dashed line object
121
. Functional block
102
connecting node
120
and
121
, i.e., FB
1
, is converted to the path connecting the nodes
120
,
121
. Using the above-described procedure,
FIG. 2
is a path and node graph
200
of converted functional block graph portion
100
of FIG.
1
. The timing analysis lists each path in path and node graph
200
as a series of nodes and delay times, i.e., the time required for processing to complete during a particular path traversal.
As a result of the timing analysis, each path is categorized as passing or failing based on slack (i.e., required time for the path to perform an allocated operation less the actual performance time) or frequency (i.e., what is the maximum frequency that can be used before the path fails to perform the operation). A single functional block frequently contains many thousands of paths. Users use a static timing tool to request a report of the first N paths. Typically the timing analysis indicates some subset of the requested N paths are failing paths.
FIG. 2
is an exemplary set of nodes and paths of the portion
100
of the circuit design of FIG.
1
. Nodes A, B
1
, B
2
, C, D, E, F, G, H, and I represent the input functional block(s) to a functional block of a circuit design. B
1
and B
2
are duplicate nodes and one node (B
1
, or B
2
, as appropriate) should be investigated if the designer determines the other is failing. For instance, the functional blocks FB
1
, FB
1
A of
FIG. 1
forming the path providing input to nodes B1, B2 of
FIG. 2
may be copies of an ALU design functional block.
For illustrative purposes, it is assumed that nodes B1, B2, and F are failing nodes (dashed circles), i.e., paths containing these nodes fail to meet or exceed the timing constraints. As a result, the timing analysis for the node and path graph portion
200
of
FIG. 2
results in a passing path list of the path made up of connected nodes D, E, and F, i.e., nodes
124
,
125
, and
123
respectively. Because paths are reported from the timing analysis as a connected series of the node names of nodes making up the path separated by periods, the passing path is referred to as ‘D.E.F’. Using this identification scheme, the failing path list includes the following paths: A.B1.C, A.B2.C, D.B2.C, G.E.F, G.H.F, and G.H.I.F, respectively indicated by reference numerals
202
-
207
(shown as shaded paths).
Circuit designers receive timing analysis results identifying the nodes and paths of a circuit design, a corresponding timing delay for each path, and lists of passing and failing paths based on timing constraints for the circuit design. Because of the large number of paths in circuit designs, there are frequently large numbers of failing paths requiring correction to meet or exceed the timing constraints. Correcting each failing path in turn and re-running the timing analysis requires a large amount of time. Fortunately in many circuits, a single node can cause numerous path failures and if the particular node can be identified, the large amount of time and effort required to identify and correct several related path failures can be minimized. To this end, circuit designers use numerous approaches, e.g., rules of thumb, designer intuition, circuit topology knowledge, and engineering judgment, to minimize the amount of time and effort required to identify defective nodes and ultimately circuit designs.
One method used by circuit designers to reduce the number of failing paths is grouping related failing paths into sets. These groupings, i.e., sets of failing paths, are sometimes referred to as ‘buckets’ by circuit designers and the process of grouping the failing paths is referred to as ‘bucketizing’. Because a node can occur in many paths, a single bad node delay, resulting, e.g., from a driver too small for output loading thereof, might cause many paths to fail. Fortunately, in many cases, a single fix to a particular functional block corresponding to the bad node can simultaneously fix all the remaining failing paths which include the node.
Another method used by circuit designers to reduce the number of failing paths under consideration for correction is common grouping of nodes corresponding to common functional blocks. Most often, common grouping is related to bus lines on integrated circuit designs. If a single line of a bus has a problem, e.g., a particular functional block for driving a signal on a particular line, often every line of the bus has the same problem because the particular functional block is frequently duplicated for all lines of the bus. With reference to
FIG. 2
, common grouping might be employed by a designer to group paths containing B1 and B2, i.e., FB
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