Failure-analyzing semiconductor device and semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S313000

Reexamination Certificate

active

06710393

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a failure-analyzing semiconductor device having memory cells and a method of manufacturing a semiconductor device using the failure-analyzing semiconductor device. More specifically, the present invention relates to a failure-analyzing semiconductor device adapted to monitor the process, yield and reliability in a factory on a regular basis and a method of manufacturing a semiconductor device using the failure-analyzing semiconductor device.
2. Description of the Related Art
Conventionally, in a production line for semiconductor devices, failure-analyzing LSIs (large-scale integrated circuits) have been produced on a regular basis in addition to LSI products for sale. These LSIs are used to improve the yield in the semiconductor device production line or to test the reliability on behalf of products.
For example, in the manufacture of SRAMs (static random access memories), failure-analyzing LSIs (hereinafter referred to as SRAM-TEG (test element group)) each having an SRAM cell array and a test pattern formed have been used.
With the use of the SRAM-TEG, when failures have occurred, a memory test can be made to identify defective cells. Also, the SRAM-TEG, being simple in structure, allows ease of identification of defective regions and analysis of causes. The introduction of an FBM (fail bit map) system has made the identification and analysis of defective cells and regions still easier.
The FBM is a system which represents memory cells in rows and columns according to their physical arrangement and displays defective cells and non-defective cells. In the FBM, defective cells are divided into a number of failure categories according to their arrangement. The failure categories are patterns of arrangement of defective bits (defective cells) detected by the FRB system. The failure categories vary according to interconnection structures of SRAMs.
A conventional failure-analyzing LSI will be described with some accompanying drawings.
FIG. 1A
is a plan view of interconnection patterns of the conventional failure-analyzing LSI.
FIG. 1B
schematically shows, in a sectional view, the structure of the failure-analyzing LSI.
As shown in
FIG. 1B
, a semiconductor substrate
51
has diffused regions (active regions)
52
formed therein. On the opposite sides of each diffused region are formed two memory cells (not shown). Memory cells corresponding to eight bits are formed for four diffused regions
52
.
Over the semiconductor substrate
51
are formed sequentially first-level interconnect patterns (not shown) and a second-level interconnect patterns (in the drawing, a bit line pattern
53
A is shown) with an insulating film interposed therebetween. The bit line pattern
53
A is connected to the diffused regions
52
through via holes
54
.
FIG. 1B
is a sectional view of the bit line pattern
53
A of the failure-analyzing LSI along the column direction.
As the second-level interconnect patterns, as shown in
FIG. 1A
, /bit line patterns
53
B and reference-potential line patterns
53
C are formed in addition to the bit line patterns
53
A. The bit line patterns
53
A and the /bit line patterns
53
B are interconnections which are supplied with different potentials each of which is the inverse of the other. The bit line patterns
53
A and the /bit line patterns
53
B are supplied with a write signal or read signal in a read operation or write operation. The reference potential line patterns
53
C are supplied with a reference potential.
In such a failure-analyzing LSI, failures which occur in the bit line patterns
53
A, the /bit line patterns
53
B and the reference potential line patterns
53
C are detected by the FBM. For example, in the event of a short circuit between each pattern, the FBM becomes as depicted in FIG.
2
.
Next, another conventional failure-analyzing LSI will be described.
FIG. 3A
is a plan view of interconnection patterns of the conventional failure-analyzing LSI.
FIG. 3B
schematically shows, in a sectional view, the structure of the failure-analyzing LSI.
As shown in
FIG. 3B
, as in the aforementioned failure-analyzing LSI, the semiconductor substrate
51
has diffused regions (active regions)
52
formed therein. Memory cells corresponding to eight bits are formed for four diffused regions
52
.
Over the semiconductor substrate
51
are formed sequentially first-level interconnect patterns (not shown), second-level interconnect patterns (in the drawing, the bit line pattern
53
A is shown) and third-level interconnect patterns (in the drawing, a bit line pattern
55
A is shown) with an insulating film interposed between each interconnect pattern. The bit line pattern
53
A is connected to the diffused regions
52
through via holes
56
. The bit line pattern
55
A is connected to the bit line pattern
53
A through via holes
57
.
FIG. 3A
shows only the second- and third-level interconnect patterns. As the second-level interconnect patterns, /bit line patterns
53
B and reference-potential line patterns
53
C are formed in addition to the bit line patterns
53
A. As the third-level interconnect patterns, /bit line patterns
55
B are formed in addition to the bit line patterns
55
A.
The bit line patterns
53
A and the /bit line patterns
53
B are interconnections which are supplied with different potentials each of which is the inverse of the other. The bit line patterns
53
A and the /bit line patterns
53
B are supplied with a write signal or read signal in a read operation or write operation. The reference potential line patterns
53
C are supplied with a reference potential. Likewise, the bit line patterns
55
A and the /bit line patterns
55
B are interconnections which are supplied with different potentials each of which is the inverse of the other. The bit line patterns
55
A and the /bit line patterns
55
B are supplied with a write signal or read signal in a read operation or write operation. The reference potential line patterns
53
C are supplied with a reference potential.
In such a failure-analyzing LSI, failures which occur in the second-level line patterns
53
A,
53
B and
53
C and the third-level line patterns
55
A and
55
B are detected by the FBM. For example, in the event of a short circuit between the second-level line patterns or the third-level line patters, the FBM will show the same failure category as depicted in FIG.
2
.
However, the failure-analyzing LSI shown in
FIG. 1B
has a problem that since the density of interconnections, such as the bit line patterns
53
A, the /bit line patterns
53
B and the reference potential line patterns
53
C, in the memory cell array is low and there is little minimum space between each interconnection, the rate of detection of a short circuit between each interconnection is low.
In the failure-analyzing LSI shown in
FIG. 3B
, the failure category detected by the FBM in the event that the second-level bit line patterns
53
A and
53
B are short-circuited is the same as in the event that the third-level bit line patterns
55
A and
55
B are short-circuited. For this reason, a layer in which a failure has occurred cannot be identified. That is, even with different defective regions or different causes of failure, the FBM indicates the same failure category, making it difficult to identify defective regions or causes of failure. Therefore, physical analysis of defective regions is required.
In LSIs, multilevel interconnections have been increasingly used. In failure-analyzing LSIs (SRAM-TEG and the like) as well, multilevel interconnections are being adopted accordingly. This results in an increase in the probability of different defective regions or different causes of failure being indicated as the same failure category.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which saves the necessity of physical analysis of defective regions and allows the time required for failure analysis to be reduced and the rate of failure detection to be improved.
It

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