Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-11-27
2004-08-24
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S207000, C257S211000
Reexamination Certificate
active
06781151
ABSTRACT:
BACKGROUND OF THE INVENTION
a. Field of the Invention
The present invention pertains to integrated circuit manufacturing and specifically to test samples used to qualify a new manufacturing process.
b. Description of the Background
In the development of a new manufacturing process for integrated circuits, certain design rules are created that define the capabilities of the process. A designer begins the design of new integrated circuits at the same time as the manufacturing capability is being developed. The concurrency of new process development and product design places great importance on the ability of the manufacturing process to be able to produce integrated circuits using those design rules.
The design rules include such things as minimum trace width, minimum distance between traces, the maximum number of vias that may be stacked on top of each other, and other such parameters. Typically, a manufacturer may guarantee that a process will manufacture good parts if the parts conform to the design rules, thus allowing the designers to begin integrated circuit designs many months before the manufacturing process is ready.
After the first production of a new integrated circuit design, there is generally a period of failure analysis as the design and manufacturing processes are adjusted to produce a successful product. The root cause failure analysis of some integrated circuits may be very time consuming, sometimes consuming days or even weeks to isolate a single fault on a single chip.
The failure analysis techniques available to development engineers include mechanical probing, optical beam induced current (OBIC), optical beam induced resistive change (OBIRCH), picosecond imaging circuit analysis (PICA), light induced voltage alterations (LIVA), charge induced voltage alterations (CIVA), various scanning electron microscopy techniques, and other techniques known in the art. In addition, destructive tests, such as etching and lapping, may be used to isolate and identify problems.
In many cases, the design of an integrated circuit may limit or prohibit certain techniques for ascertaining faults. For example, in order to probe a certain path using a laser technique, the path must not have another metal trace directly above the path of interest. Further, the various techniques may only isolate a problem within a certain section of the circuitry, but not to a specific trace or via.
During process development and verification, it is important that faults are isolated to the exact location. For example, a via may have very high resistivity. In order for the manufacturing process to be corrected, the location of the via must be identified exactly. Failure analysis techniques that isolate only a section of a electric path is not sufficient for the fine tuning of the manufacturing process.
It would therefore be advantageous to provide a system and method for testing an integrated circuit manufacturing process wherein a multitude of failure analysis techniques may be used to quickly isolate a manufacturing defect. It would further be advantageous if the system and method were able to stress the manufacturing process by operating at the design limits of the manufacturing process.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages and limitations of the prior art by providing a system and method for exercising an integrated circuit manufacturing process while allowing failure analysis access to as many individual connections and components as possible. Further, the present invention may be used to test static performance using direct current as well as dynamic performance with high-speed operational frequencies. An integrated circuit designed at many of the manufacturing process limits offers complete and fast failure analysis so that manufacturing defects can be quickly found and the process improved.
The present invention may therefore comprise an integrated circuit testable serpentine staircase for an integrated circuit comprising a plurality of interconnect layers, the staircase comprising: a first power bus having a first axis; a second power bus parallel to the first axis; an input signal trace on a first layer disposed between the first power bus and the second power bus; a series of successive layers wherein each layer comprises an elongate first bus power trace extending substantially perpendicular from the first axis and electrically connected to the first power bus, an elongate second bus power trace extending substantially perpendicular from the first axis and electrically connected to the second power bus, and a signal trace disposed between the first power trace and the second power trace at a predetermined distance from the first power trace to the signal trace and at the predetermined distance from the second power trace to the signal trace, wherein the signal trace from one layer is connected to the signal trace of the next layer by a via, wherein the via does not have any other traces above the via, wherein at least a portion of the signal traces has no other traces above the signal trace, the signal traces adapted to be electrically connected to the input signal trace on the first layer, the signal traces further adapted to be electrically connected to each of the layers in succession from the first layer to an upper layer; and a plurality of test pads located on the top layer adaptable to probing wherein each of the test pads is electrically connected to the signal traces on each of the layers.
The present invention may further comprise a test vehicle for an integrated circuit comprising: an input signal wire; an output signal wire; and a plurality of unit delay cells comprising a unit cell input, a unit cell output, and a plurality of integrated circuit functional cells, each of the functional cells being connected by a staircase to the next of the functional cells, the staircase comprising a first power bus having a first axis, a second power bus parallel to the first axis, an input signal trace on a first layer disposed between the first power bus and the second power bus, a series of successive layers wherein each layer comprises an elongate first bus power trace extending substantially perpendicular from the first axis and electrically connected to the first power bus, an elongate second bus power trace extending substantially perpendicular from the first axis and electrically connected to the second power bus, and a signal trace disposed between the first power trace and the second power trace at a predetermined distance from the first power trace to the signal trace and at the predetermined distance from the second power trace to the signal trace, wherein the signal trace from one layer is connected to the signal trace of the next layer by a via, wherein the via does not have any other traces above the via, wherein at least a portion of the signal traces has no other traces above the signal trace, the signal traces adapted to be electrically connected to the input signal trace on the first layer, the signal traces further adapted to be electrically connected to each of the layers in succession from the first layer to an upper layer, and a plurality of test pads located on the top layer adaptable to probing wherein each of the test pads is electrically connected to the signal traces on each of the layers.
The present invention may further comprise a method of testing a manufacturing process comprising: designing a test vehicle, the test vehicle comprising an input signal wire, an output signal wire, and a plurality of unit delay cells comprising a unit cell input, a unit cell output, and a plurality of integrated circuit functional cells, each of the functional cells being connected by a staircase to the next of the functional cells, the staircase comprising a first power bus having a first axis, a second power bus parallel to the first axis, an input signal trace on a first layer disposed between the first power bus and the second power bus, a series of successive layers wherein each layer comprises an elongate first bus power trace ext
Howard Steve
Schultz Richard
LSI Logic Corporation
Ngo Ngan V.
The Law Offices of William W. Cochran, LLC
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