Failure analysis system, method for managing estimated logic...

Details Failure analysis system, method for managing estimated logic... Failure analysis system, method for managing estimated logic...

1999-03-25

2002-06-04

Myers, Paul R. (Department: 2181)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C706S050000

Reexamination Certificate

active

06401219

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a failure analysis for a semiconductor integrated circuit device and, more particularly, to a failure analysis system, a method for managing estimated logic status and an information storage medium for storing programmed instructions of the method.
DESCRIPTION OF THE RELATED ART
A method for managing estimated logic status is available for a failure analysis system for a sequential circuit disclosed, by way of example, in Japanese Patent Publication of Unexamined Application No. 8-146093. In the following description, term “combinational circuit” expresses a combination of component circuits of an integrated circuit. The prior art failure analysis system backwardly traces a propagation path from a defective output toward an origin of trouble, and dynamically extracts combinational circuits possibly propagating the trouble. The prior art failure analysis system evaluates the extracted combinational circuits, and gives estimated logic status to the extracted combinational circuit. The logic status is given to not only signal lines but also all nodes in the extracted combinational circuit. Signal lines, gates and input/output nodes are examples of the node to be evaluated. The logic status is represented by more than two logic values, i.e., logic “0”, logic “1”, X which means “don't care”, Z which means high-impedance and U which means undefined. When the extracted combinational circuits are linked by using the logic status, the logical link is expected to guide the analyst to the origin of trouble.
An estimated linkage of logic status of each combinational circuit is managed by using the prior art method for managing estimated logic status. Pieces of status information representative of the logic status are registered, retrieved and selectively canceled, and are formed into a tree-like index structure. A large scale integration has a large number of combinational circuits, and more than one logic value is possibly given to each combinational circuit. For this reason, the tree-like index structure for the large scale integration is huge, and the relation between the pieces of status information is less clear to an analyst.
FIG. 1
illustrates a prior art failure analysis system for the estimated logic status. The prior art failure analysis system is broken down into an input-output unit
1
, a data processing unit
2
and a memory unit
3
. Input data is supplied from the outside through the input-output unit
1
to the data processing unit
2
. The data processing unit
2
sequentially executes programmed instructions for a failure analysis, stores pieces of status information for a combinational circuit and a tree-like index structure representative of the logic status in the memory unit
3
, and delivers data to be required through the input-output unit
1
b.
The input-output unit
1
includes a data input unit
1
a
and a data output unit
1
b
. The input unit
1
a
is a keyboard and a data interface to a diagnostic system (not shown). The output unit
1
b
is a printer and a data interface to the diagnostic system. The memory unit
3
includes a memory
3
a
for data information representative of the logic status of combinational circuits and a memory
3
b
for storing the tree-like index structure. Each of the pieces of status information represents the logic status at a node in a combinational circuit, and the logic status is labeled with an index. A logic value is given to the logic status, and the logic values are logic “1”, logic “0”, X which means “don't care”, Z which means high-impedance and U which means undefined. The node means a signal line, a gate, a gate terminal and an input/output terminal of a component circuit. On the other hand, the tree-like index structure is stored in the memory unit
3
b
. The tree-like index structure is built for each combinational circuit, and represents a linkage of logic status between the nodes.
The data processing unit
2
includes an instruction analyzer
2
a
connected to a program memory (not shown), an index marker
2
b
, a condition analyzer
2
c
for retrieving conditions and a condition analyzer
2
d
for deleting conditions. The index marker
2
b
, the condition analyzer
2
c
and the condition analyzer
2
d
are respectively accompanied with a register
2
e
, a retriever
2
f
and a deleting means
2
g.
The instruction analyzer
2
a
analyzes an instruction supplied from the input unit
1
a
, and the data processing unit selectively branches the control to a data registration, a data retrieval and a data deletion. In other words, the control sequence is transferred from the instruction analyzer
2
a
to the index marker
2
b
, the retrieving conduction analyzer
2
c
or the condition analyzer
2
d.
The index marker
2
b
adds an index to the logic status given to a node or a group of nodes to be registered, and transfers the piece of status information representative of the logic status labeled with the index to the register
2
e
. The index is representative of both of a name of nodes in the combinational circuit and a relation between the nodes. If nodes are branched from a node, the nodes respectively have sub-indexes branched from an index given t o the node. A name is given to each node, and the name of node is also stored so as to make the linkage clear. The register
2
e
assorts the pieces of status information by the index, and stores the pieces of status information together with the names of the associated nodes. Moreover, the register
2
e
builds the pieces of status information into a tree-like index structure, and stores the tree-like index structure in the memory unit
3
b
. While the register
2
e
is building the pieces of status information into the tree-like index structure, the sub-indexes are located under the index. Thus, lower-level indexes are branched from an upper-level index, and all the indexes are built into the tree-like index structure.
The condition analyzer
2
c
determines search conditions for a data retrieving to be requested, and supplies the search conditions to the retriever
2
f
. The retriever
2
f
searches the memory units
3
a
/
3
b
for a piece or pieces of status information satisfying the search conditions, and supplies the search result to the output unit
1
b.
The condition analyzer
2
d
determines search conditions for a deletion of a piece of or pieces of status information from the contents of the memory units
3
a
/
3
b
, and supplies the search conditions to the deleting means
2
g
. The deleting means
2
g
deletes a piece of pieces of status information satisfying the search conditions from the contents of the memory units
3
a
/
3
b.
FIG. 2
illustrates the control sequence achieved by the prior art failure analysis system, and
FIG. 3
illustrates a tree-like index structure built by the prior art failure analysis system. The tree-like index structure is finally achieved through repetition of the control sequence shown in FIG.
2
. F
1
to F
16
are indicative of the names of nodes incorporated in a combinational circuit, and numeral “0” in a circle to numeral “15” in a circle are representative of the indexes each given to a group of nodes such as (F
1
, F
2
).
FIG. 4
shows a logic path from the index “0” through the indexes “1” and “3” to the index “6” and the index “8” in the tree-like index structure, and
FIG. 5
shows another logic path from the index “0” through the indexes “1” and “4” to the index “10” and the index “12” in the tree-like index structure. The logic paths are determined through the execution of the program sequence shown in FIG.
2
.
The prior art control sequence is firstly described hereinbelow. Assuming now that a programmed instruction code is supplied from the input unit
1
a
to the instruction analyzer
2
a
, the instruction analyzer
2
a
sequentially checks the instruction code at steps SP
1
/SP
2
/SP
3
, and transfers the control to the index marker
2
b
, the condition analyzer
2
c
and the condition analyzer
2
d
. In detail, the instruction analyzer
2
a
fir

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