Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2002-11-06
2004-11-16
Boudreau, Leo (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C714S723000, C438S014000
Reexamination Certificate
active
06819788
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a failure analysis method, especially for memory LSIs.
2. Description of the Background Art
Generally, memory LSIs have a memory cell array having a pattern in which a plurality of memory cells are arranged in a matrix. One of conventionally known failure analysis methods for such memory LSIs is to use an LSI tester.
Hereinbelow, a brief outline of the conventional failure analysis methods will be described. First, using an LSI tester, all memory cells are tested for electrical characteristics. According to the test results, a first FBM (fail bit map) is generated. The first FBM has a pattern in which, in an X-Y coordinate space where row and column directions are defined respectively as X and Y directions, a plurality of bits are arranged in a matrix in correspondence with the pattern of a memory cell array.
The first FBM is then compressed with a predetermined compression ratio to generate a second FBM. When the first FBM is compressed with, for example, 8×8 bits per pixel, 64 bits (8 bits in the X direction×8 bits in the Y direction) in the first FBM correspond to one pixel in the second FBM. If any one of the 64 bits is a failure bit, a pixel corresponding to those 64 bits is set as a defective pixel, whereas if none of the 64 bits are failure bits, the pixel corresponding to the 64 bits is set as a non-defective pixel.
Then, according to a pattern of defective pixels in the second FBM, a process for recognizing the types of failures is performed. Thereby, failures are classified into several failure modes such as block, line and bit failures. Then, for each of the failure modes in the classification, a recognition process is performed based on the first FBM on a bit by bit basis, thereby to obtain detailed failure information (such as addresses and sizes).
According to the conventional failure analysis methods, however, the compression ratio in compressing the first FBM into the second FBM is a fixed value and is set somewhat higher (about 8×8 bits per pixel) in order to reduce the amount of data to be processed. Thus, depending on the conditions of a distribution of failure bits, failure mode classification may not be performed properly.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a failure analysis method that allows high-precision failure mode classification.
According to an aspect of the present invention, the failure analysis method comprises the following steps (a) to (e). The step (a) is to generate a first FBM (Fail Bit Map) having a pattern in which a plurality of bits are arranged in a matrix, based on a result of a predetermined test on an object to be tested. The step (b) is to generate a second FBM by compressing the first FBM with a first compression ratio. The step (c) is to determine an area where a failure bit exists in the first FBM, based on the second FBM. The step (d) is to generate a third FBM by compressing a portion of the first FBM which corresponds to the area, with a second compression ratio lower than the first compression ratio. The step (e) is to determine the failure bit based on the third FBM.
The determination of failure bits is performed not based on the rough second FBM but based on the third FBM finer than the second FBM. This allows high-precision determination of failure bits.
Besides, the third FBM is generated by compressing only a portion of the first FBM which corresponds to an area where a failure bit exists with a second compression ratio, rather than by merely reducing the first compression ratio. This minimizes an increase in the amount of data to be processed, thereby preventing a considerable extension of the time required for recognition.
According to another aspect of the present invention, the failure analysis method comprises the following steps (a) to (e). The step (a) is to generate a first FBM (Fail Bit Map) having a pattern in which a plurality of bits are arranged in a matrix, based on a result of a predetermined test on an object to be tested. The step (b) is to generate a second FBM having a first pattern by compressing the first FBM. The step (c) is to generate a third FBM having a second pattern different from the first pattern, by compressing the first FBM. The step (d) is to determine a first failure based on the second FBM. The step (e) is to determine a second failure based on the third FBM.
By compressing the first FBM to generate the second and third FBMs having different patterns, the first and second failures can be determined individually. For example, a line failure (first failure) can be determined based on the second FBM having the first pattern in which a plurality of strip pixels are arranged, while a bit failure (second failure) can be determined based on the third FBM having the second pattern in which a plurality of pixels are arranged in a matrix.
According to still another aspect of the present invention, the failure analysis method comprises the following steps (a) to (g). The step (a) is to generate a first FBM (Fail Bit Map) having a pattern in which a plurality of bits are arranged in a matrix, based on a result of a predetermined test on an object to be tested. The step (b) is to generate a second FBM by compressing the first FBM with a first compression ratio. The step (c) is to determine an area where a failure bit exists in the first FBM, based on the second FBM. The step (d) is to generate a third FBM having a first pattern by compressing a portion of the first FBM which corresponds to the area. The step (e) is to generate a fourth FBM having a second pattern different from the first pattern, by compressing a portion of the first FBM which corresponds to the area. The step (f) is to determine a first failure based on the third FBM. The step (g) is to determine a second failure based on the fourth FBM.
By compressing the first FBM to generate the third and fourth FBMs having different patterns, the first and second failures can be determined individually. For example, a line failure (first failure) can be determined based on the third FBM having the first pattern in which a plurality of strip pixels are arranged, while a bit failure (second failure) can be determined based on the fourth FBM having the second pattern in which a plurality of pixels are arranged in a matrix.
Besides, generating the third and fourth FBMs for only a portion corresponding to the area where a failure bit exists minimizes an increase in the amount of data to be processed.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5644578 (1997-07-01), Ohsawa
patent: 5828778 (1998-10-01), Hagi et al.
patent: 5907515 (1999-05-01), Hatakeyama
patent: 6016278 (2000-01-01), Tsutsui et al.
patent: 6564346 (2003-05-01), Vollrath et al.
Boudreau Leo
Sherali Ishrat
LandOfFree
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