Failure analysis memory for semiconductor memory testing...

Details Failure analysis memory for semiconductor memory testing... Failure analysis memory for semiconductor memory testing...

1998-11-03

2002-04-16

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06374378

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a failure analysis memory for storing information on memory cells found defective in a logical comparison test on semiconductor memories through the use of test patterns. The invention also pertains to a method for storing required information on the failed memory cells in the failure analysis memory.
DESCRIPTION OF THE PRIOR ART
FIG. 1
illustrates in block form the basic configuration of a conventional memory testing device. The memory testing device comprises a timing generator
11
, a pattern generator
12
, a waveform shaper
13
, a logic comparator
15
and a failure analysis memory
16
, and makes a test on a memory under test
14
.
Based on a reference clock generated by the timing generator
11
, the pattern generator
12
produces an address signal ADR, test data DAT and a control signal CONT which are provided to the memory under test
14
.
These signals ADR, DAT and CONT are shaped by the waveform shaper
13
into waveforms necessary for test and then applied to the memory under test
14
. Under the control of the control signal CONT the test data DAT is written in and read out of the memory
14
. The test data DAT read out of the memory
14
is fed to the logic comparator
15
for comparison with expectation data PDAT available from the pattern generator
12
to check for a mismatch therebetween and hence make a pass/fail decision on the memory under test
15
. If a mismatch is found, then fail data is stored in the failure analysis memory
16
.
FIG. 2
depicts the general configuration of the conventional failure analysis memory
16
. The failure analysis memory
16
comprises an address select part
16
A, a memory control part
16
B and a memory part
16
C. The memory part
16
C is accessed by a lower address signal from the address select part
16
A. The address select part
16
A is designed to be capable of arbitrarily selecting individual address signals ADR available from the pattern generator
12
; the upper address signal is applied to the memory control part
16
B and the lower address signal to the memory part
16
C. The memory control part
16
B responds to fail data FLA from the logic comparator
15
to apply a write signal to the memory part
16
C, and responds to the upper address signal to select a cell in the memory
16
C where to store failure information on the memory under test
14
. After the test, the stored contents of the memory part
16
C are checked for a failed address in the memory under test
14
.
Current-day IC memories are becoming increasingly high in capacity and in integration density. With a system which would reject an IC memory in its entirety as defective if even one failed cell is found, it is impossible to increase the productivity (manufacturing yield) of IC memories. In view of this, recent IC memories have a redundant configuration intended to save or repair their failed cells.
The redundant configuration is one that the IC memory has built-in spare cells in preparation for replacement for failed cells during the manufacturing process to avoid rejection of the whole IC memory as being defective and hence improve productivity. Semiconductor IC testers utilize the failure analysis memory to make a repair analysis for detecting a defective cell and replacing it with a spare cell.
In
FIG. 3A
there is depicted an example of the internal configuration of the memory under test
14
which has a four-bit data width and a four-word address depth. In general, the IC memory is provided with an address decoder
14
A, a main memory cell array
14
B and a four-bit spare cell array
14
C. Based on the address signal ADR which is input into the address decoder
14
A, any one of addresses ADR
1
, ADR
2
, ADR
3
and ADR
4
of the main memory cell array
14
B is accessed to effect the writing and reading of test data to and from respective memory cells MCL of the accessed address.
When failed memory cells FMCL are found, through repair analysis using the failure analysis memory
16
, at the accessed address as indicated by hatching in
FIG. 3B
, the analytical information is used to replace the whole memory cell array MCL containing the failed cells FLMC with the spare cell array
14
C and switch the application of the address signal ADR from the former to the latter, thereby saving the IC memory
14
from being rejected as a defective. This replacement is performed using a dedicated repair unit (such as a laser trimmer or fuse system).
If all pieces of fail data on the memory under test
14
(data indicating the failed cells FLMCL) are written in the failure analysis memory
16
to make the repair analysis, the memory
16
needs to have a large capacity and the analysis takes much time. In the memory under test
14
depicted in
FIG. 3A
, the spare cell array
14
C has a line structure extending in the data-width direction so that spare cells have a one-to-one correspondence with data bits of each word. Accordingly, when even one failed cell is found in one word in its data-width direction (hereinafter referred to as an I/O direction), all cells of one word will have to be replaced with the spare cell array
14
C. What is required as information for the repair analysis is only the presence or absence of failed cells FLMCL in each word. Hence, information necessary and sufficient for the repair analysis could be obtained even by compressing all pieces of bit data in the widthwise direction of the fail data into one-bit form through their ORing by an OR gate. This will reduce the amount of time for analysis as well as the fail data size. The ORing of the bit data in the widthwise direction of the fail data to obtain new fail data will hereinafter be referred to as a fail data I/O compression.
In
FIGS. 4 and 5
there is conceptually shown a fail data compression feature built in the conventional failure analysis memory
16
.
FIG. 4
depicts the case of testing four memories
14
A to
14
D. Four logic comparators
15
A to
15
D output, as fail data FLA to FLD, the logical comparison results on the four memories under test
14
A to
14
D. Reference numerals
23
A to
23
D and
41
A to
41
D denote respective pieces of data.
These pieces of fail data FLA to FLD are input into fail data compressing/bit position setting means
20
A to
20
D, respectively, wherein each multi-bit fail data is compressed into one-bit fail data. The pieces of the thus compressed fail data FLA to FLD are written in the memory parts
16
C corresponding to the memories under test
14
A to
14
D.
FIG. 5
illustrates the configuration of the fail data compressing/bit position setting means
20
(
20
A to
20
D). The fail data compressing/bit position setting means
20
has bit position setting means
21
A to
21
D of the same number as that of bits FL
0
to FL
3
of one of the fail data FLA to FLD. The bit position setting means
21
A to
21
D have bit position setting registers
21
A to
21
D, respectively. Based on data set in the bit position setting registers
22
A to
22
D, the fail data compressing/bit position setting means
20
selects a compression or non-compression mode and sets the bit position which it outputs in the compression mode.
That is, in the case of setting “1, 1, 1, 1,” in the bit position setting register
22
A of the bit position setting means
21
A and “0, 0, 0, 0” in the other bit position setting registers
22
B to
22
D as shown in
FIG. 5
, fail data compressed in the compression mode is output as first-bit data CFL
0
of the output data. More specifically, “1's” of the respective bits of the bit position setting register
22
A are ANDed by four AND circuits
24
A with the fail data FL
0
to FL
3
. The outputs from the four AND circuits
24
A are input into an OR circuit
25
A, and the output from the OR circuit
25
A is provided as the first bit CFL
0
of the compressed fail data output signal to the memory part
16
C. Similarly, the other bit position setting means
21
B (to
21
D) also comprise the bit position setting register
22
B (to
22
D), four AND circuits
24
B (to

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