Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-03-31
2001-11-27
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S414000, C257S629000
Reexamination Certificate
active
06323505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a failure analysis apparatus of semiconductor integrated circuits with a timing failure and the method thereof, and more specifically, to a failure analysis apparatus of semiconductor integrated circuits and the method thereof for easily identifying the failure occurring region in a short time.
2. Description of the Related Art
Recently, as the density of wiring in the semiconductor integrated circuit increases, the floating capacitance has increased. Consequently, in the wafer sorting process for inspecting electrical characteristics of wafers with elements formed, the wafer manufacturing yield may be lowered by occurrence of a failure in the timing system. The characteristics of the timing failure, in general, is to be a failure occurring in the specific test pattern among the inspections of electrical characteristics. That is, when the passivation film on the surface is removed, the wafer is not rejected due to the test pattern with which the same wafer is rejected in the previous electrical characteristic inspection but when the passivation film is formed on the wafer again, the wafer is judged to be rejected.
This kind of the timing failure is assumed to occur by changes of floating capacitance between metal wirings used in the semiconductor integrated circuits by the existence or non-existence of the passivation film on the wafer, which, in turn, causes variations to the time constant of the circuit.
In order to analyze the nonconforming wafer with the timing failure, a capacitance is formed in the region desired to be analyzed, and how the timing is deviated must be observed. This kind of an analysis method for nonconforming wafer will be described as follows. First of all, in the test pattern in which the wafer is rejected, an engineer who is familiar with the circuit technology presumes possible failure places of wiring in the pellet area. Then, using lasers and so forth, a hole is provided on the passivation film on the possible failure place, and a probe needle is set up on the wiring presumed to be failure. Then, while confirming the signal passing through this wiring by an oscilloscope and so forth, via the probe needle, the failure is investigated. If the failure portion is able to be identified by this investigation, a capacitance electrode comprising W (tungsten) film and so forth, is formed on the region, and the capacitance is formed virtually, and failure analysis is carried out while judging whether the failure level degrades or not by the LSI tester.
However, the above failure analysis method has the following problems. The first problem is that the engineer in a mass-production plant is able to determine whether it is a timing failure or not but it is difficult for the engineer to identify the failure portion region and implement the subsequent failure analysis. This is because in order to presume a failure portion of the semiconductor integrated circuit based on the test pattern in which failure occurs, expertise both on the circuit and on the test patterns and circuit operations is essential.
The second problem is that it is extremely difficult to put up a probe needle on the wiring after a hole is provided using lasers and so forth, on the passivation film on the failure portion of the semiconductor integrated circuit based on the test pattern generating the failure. This is because the wiring width and distance between wirings of the semiconductor integrated circuit are less than 1 &mgr;m as refinement of elements further proceeds.
The third problem is that time for forming the W film takes 1 to 2 hours per region when the electrode such as W film and so forth, is provided on the region after identifying the failure portion. Consequently, to form the capacitance at several portions, for example, more than
8
hours are required. This is because the apparatus such as FIB (focused ion beam) or FLB (focused laser beam) used for forming the W film is a vacuum apparatus and needs time for evacuation. In addition, the difficulty of specifying the region for forming the capacitance causes the time for forming the W film to take long. As a result, one to two hours are required for forming the w film per region.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a failure analysis apparatus of semiconductor integrated circuits and the method thereof, which can shorten the time for identifying the timing failure generating portion in semiconductor integrated circuits, can carry out failure analysis in a short time, can thereby reduce occurrence of defective products at an early stage, and can improve the productivity.
The failure analysis apparatus of semiconductor circuits formed on a semiconductor substrate according to the present invention comprises a wafer stage for mounting said substrate, a solution dropping apparatus for dropping a solution on a part of the semiconductor substrate to form a test film whose dielectric constant is 2 to 5, a microscope arranged above the solution dropping apparatus and for enlarging the surface image of the semiconductor substrate, and a unit for moving the microscope and the solution dropping apparatus in the horizontal direction relative to the wafer stage.
This solution dropping apparatus can control a dropping amount of the solution in accordance with a dimension of a region where the solution is dropped. And the solution dropping apparatus may have a solution cartridge filled with the solution, and a needle mounted so as to pass through the solution cartridge. Thereby, the solution can be dropped on the semiconductor substrate while trickling along the needle. In this case, the diameter of the needle can be 0.1 to 1 mm. The solution may be polyimide solution.
The failure analysis method of semiconductor integrated circuits according to the present invention comprises a step of preparing a plurality of pellets having same wiring patterns and passivation film on the wiring patterns. Then, the passivation film on the pellet is removed, a timing failure of the pellet after removing the passivation film is measured and digitized, and a timing failure value before forming a test film whose dielectric constant is 2 to 5 is obtained. Then, test film is selectively formed on one pellet of a plurality of pellets after removing the passivation film. A timing failure of the pellet after forming the test film is measured and is digitized, and a timing failure value after forming the test film is obtained. Thereafter, the timing failure value before forming the test film is compared with the timing failure value after forming the test film. In this case, if the timing failure value after forming the test film is degraded, it is judged that failure exists in the test film forming region. If the timing failure value after forming the test film is not degraded, it is judged that failure exists in the test film unforming region. Thereafter, the test film is selectively formed on the region in one pellet of pellets which is not judged. The region is corresponding to the region judged to have failure by the step of comparing and judging. Then, a failure region is identified by alternately repeating the step of comparing and judging and the step of selectively forming the test film on the region in the other one pellet.
The plurality of pellets may be a plurality of pellet areas defined in one wafer. The step of selectively forming the test film on one pellet of a plurality of pellets after removing the passivation film may be a step of forming the test film on the region ½ of the surface of the one pellet. The step of selectively forming the test film on the region corresponding to the region judged to have failure may be a step of forming the test film on the region ½ of the region corresponding to the region judged to have the failure. However, these regions may not necessarily be a region strictly ½, but may be practically ½.
The pellet can have an input portion and an output portion, and the st
Collins D. Mark
Hutchins, Wheeler & Dittmar
NEC Corporation
Picardat Kevin M.
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