Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-01-25
2002-11-19
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000
Reexamination Certificate
active
06483346
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit devices, and more particularly to failsafe interface circuits for integrated circuit devices.
BACKGROUND OF THE INVENTION
As integrated circuit electronics become part of virtually every portable and low power electronic system, the need for efficient low voltage devices continues to grow. Where the standard operating voltage for integrated circuit components in the last decade was generally about five volts, the recent trend has been to reduce the operating voltage to three (3) volts and even 1.8 volts in an effort to make these systems more compatible with battery operation.
Many of today's electronic systems are modular and two or more subsystems require the ability to be electrically engaged and disengaged from one another while one of the subsystems is operational. This requirement, referred to as “hot plugging,” presents significant stresses on the interface circuitry due to the inconsistent application of power to the input/output pins and the supply voltage of the system which is initially powered down. Such electrical stress can damage the integrated circuit.
Integrated circuits can also suffer stress, and failure, when a voltage is applied to an input or output pin of the device which exceeds the operational voltage of the device. Under such conditions, it is desirable to operate in a manner that diverts the excess current and/or voltage away from any device which is sensitive to these extreme conditions.
Accordingly, failsafe interface circuitry to protect an electronic circuit, such as an integrated circuit, from damage during an over voltage condition or hot plugging situation is required.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for improved failsafe interface circuits. The present invention provides interface circuits, both input (receiver circuits) and output (driver) circuits, that substantially reduce or eliminate problems associated with prior interface circuitry.
In accordance with the present invention, a failsafe interface circuit is provided for an integrated circuit which has a core logic section that provides an output signal to a bond pad connection. The interface circuit includes an extended drain driver circuit operatively coupled to the bond pad. A failsafe detect circuit is included and provides a bias signal, which in the event of a failsafe event, has a voltage which is less than a voltage on the bond pad. In this respect, a failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors which form the integrated circuit. A failsafe gate switch circuit is interposed between the core logic and the extended drain driver circuit. The failsafe gate switch is responsive to the output signal from the core logic during normal operation and is responsive to the bias signal during a failsafe event. The failsafe gate switch creates a substantially open path between the bond pad and the core logic during a failsafe event. A failsafe well switch circuit provides a well voltage signal to the extended drain driver circuit. The well voltage signal has a value which is the greater of the voltage at the bond pad or a supply voltage to the integrated circuit, such that voltage stress on the extended drain driver circuit is minimized. Those devices which will be subjected to the high voltage associated with the failsafe event are formed as extended drain devices.
Preferably, the extended drain driver circuit is formed with a P-channel extended drain transistor providing an active pull-up to the bond pad and an N-channel extended drain transistor providing an active pull-down to the bond pad.
It is also preferred that the bias signal generated by the failsafe detect circuit is substantially equal to ⅔ of the voltage on the bond pad during a failsafe event.
However, this voltage can range from ½ to ¾ of the bond pad voltage and still achieve a reasonable failsafe effect.
In one embodiment, the failsafe gate switch includes a pass gate circuit interposed between the core logic and the output driver. The pass gate circuit is formed with an extended drain N-channel device having a source terminal coupled to the core logic output, a drain terminal coupled to the output driver circuit and a gate terminal coupled to supply voltage of the integrated circuit. The pass gate further includes an extended drain P-channel device having a drain terminal coupled to the core logic output, a source terminal coupled to the output driver circuit and a gate terminal coupled to a signal LO. The signal LO is generated such that the signal is low during normal operation and substantially equal to the voltage at the bond pad during a failsafe event.
In another embodiment of the present invention, a failsafe interface circuit is formed for an integrated circuit having a core logic section which receives a signal applied to a bond pad connection. The interface circuit includes an invertor circuit with an output coupled to the core logic input. An extended drain N-channel device has a source terminal coupled to the invertor input, a drain terminal coupled to the bond pad connection and a gate terminal coupled to the supply voltage of the integrated circuit. An extended drain P-channel device has a drain terminal coupled to the invertor input, a source terminal coupled to the bond pad connection and a gate terminal coupled to a signal LO. As with the previously described failsafe gate switch circuit, the signal LO is low during normal operation and substantially equal to the voltage at the bond pad during a failsafe event. A diode is included which is coupled from the invertor input to a supply voltage in the integrated circuit.
A technical advantage of the present invention includes providing an interface circuit which reliably withstands a failsafe event, whether or not power is supplied to the integrated circuit. An additional technical advantage of the present invention is that there is no substantial DC current path to the integrated circuit power supply during a failsafe event. Yet another technical advantage of the present invention is that a failsafe interface circuit is provided which is formed using thin oxide transistors.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5424659 (1995-06-01), Stephens et al.
patent: 5448198 (1995-09-01), Toyoshima et al.
patent: 5719525 (1998-02-01), Khoury
patent: 5880602 (1999-03-01), Kaminaga et al.
patent: 5933027 (1999-08-01), Morris et al.
Huffman James D.
Kunz Keith E.
Brady III W. James
Le Don Phu
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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