Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1999-01-11
2000-10-24
Tokar, Michael
Electronic digital logic circuitry
Interface
Logic level shifting
326 81, 326 21, H03K 190175, H03K 19003
Patent
active
061373117
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an failsafe interface circuit for the input and output of digital signals and a method for the failsafe operation of an interface circuit.
Currently, a variety of concepts for digital interface logic circuitry is known. Early concepts are diode-transistor logic DTL, transistor-transistor logic TTL and emitter coupled logic ECL which concepts are used with digital logic circuits as well as digital signaling between circuits and circuit boards.
Further approaches are based on MOS-processes (metal oxide semiconductor processes) which allow for advantages as higher packaging density or lower power consumption. Due to these advantages the MOS-processes now are widely used for very large scale integrated circuits such as semiconductor memories, microcomputers and circuits for the digital signal processing.
In particular the so called CMOS-technology wherein MOS-transistors of both the n-channel type and the p-channel type, i.e. PMOS-transistors and NMOS-transistors are integrated on a single chip has been proven to be extremely useful for such applications. One reason is that the combination of PMOS- and NMOS-transistors allows to achieve almost no zero signal current and a significantly reduced power loss.
Further, the transfer characteristics of circuits constituting switching circuits can be very steep in case PMOS- and NMOS-transistors are actuated reciprocally. The CMOS-technology allows for a relatively low output resistance defined through the resistance of the drain source path of the respective PMOS- and NMOS-transistors. This is a further reason why CMOS-technology has gained significant importance for the design of digital circuitry.
Typical applications are interface circuits for the transmission of digital data with a high transfer rate, e.g., the differential transmission and reception of digital data using a pair of transmission lines. Here, approaches like differential positive emitter coupled logic DPECL, low voltage differential signaling LVDC and grounded low voltage differential signaling GLVDS are used. All these approaches use differential signaling to keep differential voltages across a pair of transmission lines as low as possible. This in turn keeps the power to be transmitted over these transmission lines having low impedances within reasonable limits.
DESCRIPTION OF PRIOR ART
FIG. 18 shows an example for an interface circuit well suited for such approaches and consisting of a power supply section 400 comprising an inductance 402, one PMOS-transistor 404, and one NMOS-transistor 406. Further, the output terminals of the power supply sections are connected to the input terminals of a switching section 408 comprising two pairs of PMOS- and NMOS-transistors, each pair constituting a switching circuit 410, 412, respectively. These switching circuits are connected to two input terminals of an output section 414 again comprising two pairs of PMOS- and NMOS-transistors 416 and 418 that can be used to selectively apply the potential at the input terminals of the output section 414 to an output terminal 420. This output terminal is connected to, e.g., one line of a pair of transmission lines.
The interface circuit shown in FIG. 18 is used to output digital signals on symmetrical low impedance transmission lines or two asymmetric low impedance transmission lines. To this end the reactance circuit receives energy from a voltage source while the PMOS- and NMOS-transistor pairs 410 and 412 forward this stored energy to the output section 414 during a discharge phase. By means of appropriately setting the duration of the charging phase and the discharging phase, it is possible to provide the output section 414 with a supply voltage suitable for power efficient operation without dissipating large amounts of power and thus without generating a large amount of heat. This is a prerequisite for integrating such interface circuits into a single CMOS integrated circuit.
One problem with such interface circuits is that
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patent: 5319259 (1994-06-01), Merrill
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U. Tietz, Ch. Schenk, "Halbleiter-Schaltungstechnik,", Springer-Verlag Berlin, Heidelberg, New York 1974.
Cho James H.
Telefonaktiebolaget LM Ericsson
Tokar Michael
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