Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-06-26
2001-02-27
Hua, Ly V. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S051000, C710S120000
Reexamination Certificate
active
06195769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to transfer of data in an electronic system, and more particularly to a method and an apparatus for determining when data transferred between electronic devices that are clocked by different clock signals is corrupt.
2. Description of the Related Art
When an electronic device running at one clock frequency attempts to read data from an electronic device running at a different clock frequency, the asynchronous nature of the transaction may cause a hazard period where the data is corrupt. Such a hazard in an asynchronous circuit is an unwanted transient precipitated by unequal paths through a combinatorial network. Even when the electronic devices are running at the same clock frequency, if the clocks are not synchronized, a hazard period may exist.
There are three typical types of hazards: dynamic, static, and essential. A dynamic hazard is a multiple momentary transient in an output signal that should have changed only once in response to the input change. A static hazard is a single momentary transient in an output signal that should have remained static in response to an input change. An essential hazard is an operational error causing a transition to an improper state in response to an input change, generally caused by an excessive delay to a feedback variable in response to an input change. Hazards can cause operational problems by causing faulty state transitions in devices and presenting undesirable glitches to any device to which the hazard is connected.
A known method used to synchronize data transfer between electronic devices clocked by different clock signals was to provide an interface with multiple banks of flip-flops. In one prior art embodiment where data was transferred from a first device to a second device, a first bank of flip-flops would be clocked by a first clock signal provided by the first device. A second and third bank of flip-flops was clocked by a second clock signal provided by the second device to complete the data transfer. It would be desirable, however, to provide a technique for data transfer employing fewer gates and fewer delays.
SUMMARY OF THE INVENTION
Circuitry according to the present invention provides a data corruption indicator circuit between a first device and a second device which operate on different clock signals. The first device provides a data signal, a data ready signal, and a first clock signal to the data corruption indicator circuit. The data corruption indicator circuit provides a clocked data ready signal which is used to internally latch a status signal into a status flip-flop within the data corruption indicator circuit. The output of a potential corruption flip-flop, internal to the data corruption indicator circuit, provides the status signal. The data corruption indicator circuit also provides a delayed data ready signal. The delayed data ready signal is used to internally latch the data signal into a data flip-flop, clock the output of the potential corruption flip-flop to a high state, and may be used as an interrupt signal to alert the second device that data is available for transfer. If the interrupt signal is utilized, sometime after the second device receives the interrupt signal, it reads the latched data signal and the status signal and provides a read data signal to the data corruption indicator circuit. The read data signal resets the potential corruption flip-flop.
The new technique can reduce the amount of time required to transfer data and does reduce the number of devices required for data transfer from that in the described prior art. By flagging corrupt data, the invention ensures that a hazard will not lead to unknowingly corrupt data.
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Octal Transparent D-Type Latch with 3-State Outputs, Texas Instruments Incorporated, Copyright © 1996, pp. 1-6.
Advanced Micro Devices , Inc.
Akin Gump Strauss Hauer & Feld L.L.P.
Hua Ly V.
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