Electronic digital logic circuitry – Reliability – Fail-safe
Reexamination Certificate
2009-10-31
2010-11-16
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Reliability
Fail-safe
C326S058000, C326S086000
Reexamination Certificate
active
07834653
ABSTRACT:
A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.
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Deshpande Vani
Kothandaraman Makeshwar
Kumar Pankaj
Parameswaran Pramod Elamannu
Abhyanker, PC Raj
Cho James H.
Crawford Jason M
LSI Corporation
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