Fail safe buffer capable of operating with a mixed voltage core

Details Fail safe buffer capable of operating with a mixed voltage core Fail safe buffer capable of operating with a mixed voltage core

1999-05-25

2001-02-06

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Reliability

Fail-safe

C326S057000, C326S083000

Reexamination Certificate

active

06184700

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated circuit (IC) having a fail safe buffer that operates from a power supply different from the power supply that powers the digital core.
DESCRIPTION OF THE RELATED ART
Most IC chips can be divided into two groups of circuits. One group of circuits, called buffers, function to drive and receive signals from other IC chips. The other group of circuits, comprising the remainder of the chip (i.e., the portion of the chip not dedicated to buffers) is generally called the “core” or “core logic”.
“Fail safe” buffers are buffers that present a high impedance to a line to which they are connected (e.g., a telephone line) even when power to the buffer, generally referred to as VDD, is not present. However, many prior art fail-safe buffer designs assume that a single voltage source powers both the buffer and the core logic of the IC chip. Since many new ICs are using separate voltages for the buffers and the chip cores to save on power, it is possible that the chip core power supply may not be present while the buffer power supply is still on. This lack of power to the core logic can cause the buffer to be in a low impedance state, negating the fail-safe nature of the chip.
FIG. 1
illustrates a prior art open collector buffer as an example of a 5 volt tolerant output buffer manufactured in 3.3 volt technology (i.e., designed to tolerate a gate-source voltage or gate-drain voltage of approximately 3.3 volts). The circuit of
FIG. 1
includes an inverter
10
comprising transistors
12
and
14
. Inverter
10
also includes an input node
16
and an output node
18
. Coupled to output node
18
is a pull-down stage
20
comprising transistors
21
and
22
. Transistor
21
is connected to pad
30
via transistor
22
. The inverter
10
drives output node
18
, which in turn drives the gate of transistor
21
. Thus, when input node
16
is high, output node
18
is low and transistor
21
is off. An external resistor (not shown) which is connected between the pad and a power supply in a conventional manner pulls the pad
30
to a high voltage. If, however, input node
16
is low, output node
18
will be high, turning on transistor
21
and pulling pad
30
to a low voltage, since the conductance of the transistors
21
and
22
is much greater than that of the external pull up resistor.
Transistor
22
protects the circuit of
FIG. 1
against voltages that can cause reliability problems. The gate of transistor
22
is permanently connected to a 3.3 volt power supply, VDD. Thus, when input node
16
is high, and a 5 volt signal is present on pad
30
, transistor
22
acts as a source follower so that the voltage on node
24
cannot go above VDD−VTH
22
, where VTH
22
is the threshold voltage of transistor
22
(typically about 1 volt). Thus, node
24
will not go above 2 volts, and therefore both transistors
22
and
21
meet the reliability criteria (i.e., they do not carry voltages that exceed the 3.3 volt limitation).
The circuit of
FIG. 1
is 5 volt tolerant as long as VDD is present. However, if VDD is not present, the full 5 volts will be applied across the gate of transistor
22
, since VDD would be zero. Thus, the circuit of
FIG. 1
is not a fail-safe buffer.
FIG. 2
illustrates a modification to the circuit of
FIG. 1
which makes the circuit a fail-safe open collector output buffer. The circuit of
FIG. 2
is identical to that of
FIG. 1
, with one exception. Rather than connecting the gate of transistor
22
to VDD, in the
FIG. 2
configuration, the gate of transistor
22
is connected to a reference voltage
26
. Both the circuit of FIG.
2
and specific details regarding a reference voltage generator utilized to generate reference voltage
26
are the subject of commonly assigned co-pending patent application Ser. Nos. 09/069,049 and 09/067,818, both of which are incorporated herein by reference.
The circuit of
FIG. 2
operates as follows. When VDD is present, the voltage at reference voltage node
26
is equal to VDD. However, if VDD is not present, and a high voltage is applied to the pad
30
, the reference voltage
26
is dropped to approximately half of the voltage applied to pad
30
. Thus, if 5 volts is applied to the pad
30
, reference voltage
26
will be 2.5 volts. Therefore, the voltage across the gate of transistor
22
will also be 2.5 volts and the source-drain voltage of transistor
22
will be approximately 3.5 volts, even when VDD is not present.
Since, as noted above, many new ICs are using a lower voltage for the chip core than for the buffers to save on power, it is possible that the chip core power supply may not be present while the buffer power supply, VDD, is still on. In the circuit of
FIG. 2
, this condition will mean that node
16
, which comes from the chip core, is low. This turns transistor
21
on, causing the output, node
30
, to go low, which will cause the circuit to sink a large current, defeating the purpose of a fail-safe buffer.
SUMMARY OF THE INVENTION
According to the present invention, a buffer portion of an IC chip operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in a high impendence state, regardless of whether or not power is supplied to the core logic.
This is accomplished by constructing an integrated circuit (IC) having a buffer receiving power from a first power supply and core logic receiving power from a second power supply, and including in the IC a core-voltage blocking circuit coupled to the second power supply, wherein the output of the IC is in a high impedance state when the second power supply is not applied to the core logic.


REFERENCES:
patent: 5160855 (1992-11-01), Dobberpuhl
patent: 5446300 (1995-08-01), Amato et al.
patent: 5576635 (1996-11-01), Partovi et al.
patent: 5952866 (1999-09-01), Kothandaraman et al
patent: 5963083 (1999-09-01), Kothandaraman et al

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