Fail number detecting circuit of flash memory

Details Fail number detecting circuit of flash memory Fail number detecting circuit of flash memory

2001-11-01

2003-01-14

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185070

Reexamination Certificate

active

06507518

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device such as a flash memory and more particularly to a method which is used for detecting the result of verify readout in the programming operation and erase operation and is adequately applied to a flash memory having a large batch processing unit.
2. Description of the Related Art
In a flash memory, the effective programming speed and erase speed are enhanced by programming data in the unit of page and performing the erase operation in the unit of page or in the unit of plural pages. In the programming operation in the page unit, a program pulse applying operation and verify readout operation are performed after program data is serially input and data is input to registers of one page, and then the program pulse applying operation and verify readout operation are repeatedly performed until whole data of the page is programmed. At this time, two methods are conventionally used to determine whether whole data in the page has been programmed or not.
The first method is to detect data of the verify readout result from the all of the registers of the page since the verify readout result is latched in the registers in one page after the verify readout operation was effected after the program pulse applying operation. The first method is schematically explained with reference to FIG.
1
.
FIG. 1
is a block diagram showing a core section of a NAND flash memory. In the core section, a memory cell array
100
, input/output buffer
110
, row decoder
120
and the like are provided. The memory cell array
100
uses different I/O at the time of data input/output and is divided into a plurality of memory cell regions
100
-
0
,
100
-
1
, , . . . ,
100
-i (well regions are not divided) For example, the memory cell array is divided into regions
100
-
0
to
100
-
511
when one page is constructed by
512
columns. In
FIG. 1
, for example, the memory cell
100
which is constructed by eight I/Os is shown and data of one page is supplied via column selection gates controlled by column selection signals CSL
0
, CSL
1
, . . . , CSLi and input/output via the input/output buffer
110
(I/O
0
to I/O
7
) for each byte (for each register group
10
a
of one byte).
Each NAND memory cell
130
is configured by two selection transistors S
1
, S
2
whose gates are respectively connected to selection gate lines SGS, SGD and memory cells MC
0
, MC
1
, . . . , MC
15
whose current paths are serially connected between the selection transistors S
1
and S
2
and whose gates are respectively connected to word lines WL
0
, WL
1
, . . . , WL
15
. One end of the current path of the selection transistor S
1
is connected to a source line CELSRC and one end of the current path of the selection transistor S
2
is connected to a corresponding one of bit lines BL
0
_
0
to BL
0
_
7
. The selection gate lines SGS, SGD and word lines WL
0
, WL
1
, . . . , WL
15
are supplied with predetermined voltage from the row decoder
120
.
The bit lines BL
0
_
0
to BL
0
_
7
are respectively connected to registers (page buffers) P/B_
0
to P/B_
7
which temporarily hold program data. The registers P/B_
0
to P/B_
7
respectively correspond to the data input/output buffers I/O
0
to I/O
7
and correspond to the same address in the register group
10
a
of one byte. Since registers P/B which are connected to other bit lines BLi_
0
to BLi_
7
in the same manner as described above are provided, registers of the same number are connected for memory cells of one page which are dealt with as a programming unit (i.e.
512
Byte).
Each of the registers P/B_
0
to P/B_
7
is used for performing both of the operations for holding program data and holding readout data and the verify readout result is held in each of the registers P/B_
0
to P/B_
7
. Therefore, information on whether whole data in one page could be programmed or not can be acquired by reading out and supplying data of the registers P/B_
0
to P/B_
7
to signal lines DIO
0
to DIO
7
and directly counting a data number (which is hereinafter simply referred to as a fail number) corresponding to the number of programming fails. In the first method, time for reading out whole data of the registers in one page is required, but it is possible to specifically acquire information on the fail number by use of a counter circuit (not shown) or the like.
On the other hand, the second method is to detect output nodes of registers in one page based on the OR logic. This example is explained with reference to FIG.
2
. In the example of
FIG. 2
, signal lines (nodes) COM
0
, COM
1
, . . . , COMi used for outputting data after the verify readout operation are led out from the register group
10
a
of one byte and respectively connected to the gates of PMOS (P-channel MOS) transistors
22
-
0
to
22
-i and the PMOS transistors
22
-
0
to
22
-i are connected together via fuse elements (Fuse)
21
-
0
to
21
-i in a wired OR configuration. The current path of an NMOS (N-channel MOS) transistor
300
is connected between a common node LSEN of the fuse elements
21
-
0
to
21
-i and the ground node and the gate thereof is controlled by a detection signal VERIFY. Before the detection operation, the signal VERIFY is controlled and set at the “H” level and the common node LSEN is set at an “L” level.
The fuse elements
21
-
0
to
21
-i are provided to separate a defective column which cannot be used for correctly programming data from the detection operation. In a case where the signal VERIFY is set to the “L” level, the register group
10
a
of each column is connected to the signal lines COM
0
to COMi of each column at preset timing and an “L” level is output to a signal line COMj (
0
≦j≦i) of a certain column, then the common node LSEN is charged from the “L” level set in the initial state to the “H” level via the PMOS transistor
22
-j and fuse element
21
-j. Since current passage circuits respectively formed by serially connecting the PMOS transistors
22
-
0
to
22
-i and the fuse elements
21
-
0
to
21
-i are connected in parallel, the common node LSEN cannot be maintained at the “L” level if the signal lines COM
0
to COMI of all of the columns do not output the “H” level. Therefore, whether or not pass results of verify readout are held in all of the registers can be detected by making such a construction that data of the register
10
b
which holds the fail result is output to the signal line COMj as the “L” level. With the above method, a period required for outputting data from the register group
10
a
to the signal lines COM
0
to COMi and a period required for determining the potential of the common node LSEN can be made short and the presence or absence of the program fail state can be detected by the batch processing operation.
However, in the case of the first method, it takes a long time to acquire the result, and in the case of the second method, only information that all of the columns in the page have passed can be acquired.
When the fail number detecting operation is performed in the erase operation or during the normal program operation, the operation speed of the second method is high and it is functionally sufficient. However, when a defective column is contained, the second method can be functionally used only after cutting off a fuse element among the fuse elements
21
-
0
to
21
-i which corresponds to the defective column. This is because a defective column section continuously holds fail data in some cases. Therefore, a test process which can be performed only after cutting off the fuse element is provided, the efficiency is lowered.
Further, the state may be permitted as the pass state in some cases if an error correction function is provided inside or outside the semiconductor memory device and the number of fails occurring in the program operation or erase operation is smaller than a preset number within a range of the error correction processing ability. In this case, it is possible to detect a preset number of fails by use of the first

Affiliated with

Also associated with

Rating

Fail number detecting circuit of flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fail number detecting circuit of flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fail number detecting circuit of flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3059182