Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-09-27
2001-04-17
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S194000
Reexamination Certificate
active
06219287
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to, in a memory device test apparatus, a fail memory circuit in which the failure information (fail data) is stored, and an interleave copy method of the fail memory circuit.
In the recent memory device, in accompany with the increase of the performance of the general purpose devices, the capacity and the speed are greatly increased. In order to analyze the failure information (fail data) of a device by the device test, a fail memory circuit to store the fail data exists in a memory tester.
FIG. 4
is a block diagram of the conventional fail memory circuit.
Numeral
6
is a test apparatus to test the measured device, and outputs an address of a portion in which a failure occurs, and the result of the test as the fail data to a fail memory circuit
1
. Numeral
7
is a pattern generation circuit to output a test address AD. The fail memory circuit
1
stores the fail data FD inputted from the test apparatus
6
in memory units A -D in real time.
Incidentally, the fail memory circuit
1
stores the fail data FD by an interleave method so that the writing of the fail data FD is conducted at high speed. Thereby, each memory unit operates at the frequency of (test frequency/memory unit number).
Numeral
2
a memory which, when the input is received from a device selection signal generation circuit
9
, is in an operating condition, and corresponding to the input signal from a writing signal generation circuit
8
, the read mode/write mode is switched.
Numeral
60
is a Dout control circuit by which, when the data is inputted from a memory
2
, the data is converted into a form conformable to an input of an OR circuit
70
. Further, the memory units A -D are respectively the same structure. Numeral
70
is an OR circuit by which the data outputted from each Dout control circuit
60
are OR-operated. Numeral
4
is a data control circuit by which, when the data is inputted from the OR circuit
70
, the data is converted into a form conformable to an input of a memory array
3
.
Incidentally, in order to convert the fail data obtained by the test into the data necessary for the failure analysis of the device, the processing (interleave copy) to collect together the fail data which is processed in parallel, is necessary. Referring to
FIGS. 5A and 5B
, this interleave copy method will be described below. Incidentally,
FIG. 5A
is a simplified circuit of the fail memory circuit
1
in FIG.
4
.
An address circuit
10
generates an address a
1
at time t
1
, and outputs the address a
1
as an output signal A
1
to an address control circuit
5
. The address control circuit
5
outputs the inputted address a
1
as an output signal A
2
to the memory array
3
at time t
3
. In this case, the address generation circuit
10
outputs the address a
1
from time t
1
to time t
7
, and according to that, the address control circuit
5
outputs the address a
1
from time t
3
to time t
9
.
The memory array
3
outputs the fail data d
1
-
1
-dl-
4
stored in the memory address al of the memory units A -D as the output signals D
1
-
1
-D
1
-
4
to the OR circuit
70
at time t
5
, when the address a
1
is inputted. The OR circuit
70
OR-processes the inputted fail data d
1
-
1
-d
1
-
4
into the fail data d
1
, and outputs the fail data d
1
to the data control circuit
4
.
The data control circuit
4
outputs the inputted fail data d
1
to the memory array
3
at time t
8
. The memory array
3
overwrites, when the fail data d
1
is inputted, the fail data d
1
on the address al of the memory units A -D. By these sequential operation, the interleave copy is conducted.
Herein, the address of each memory units A -D in which the OR-processed fail data is written, is the same as the address at the time of the reading of the fail data. Accordingly, in the above described conventional circuit, when the interleave copy is conducted, the same address is continuously outputted from the time of the reading of the fail data to the time of the writing of the OR-processed fail data into each memory unit, (from t
4
to t
9
).
As the result, in the conventional circuit, when the necessary number of clock stages from the read mode to the write mode is N, the processing time of the following expression is necessary for the interleave copy:
(rate) ×(N +2) ×(memory capacity) [nS]
As described above, in the fail memory circuit, it is necessary that the fail data which is written by the interleave method, is OR-processed and collected together, and written into the memory unit again. In the conventional method, because during the time of transferring from read mode to write mode, the same address are continuously outputted, and thereby, the interleave copy is conducted, the processing time proportional to the number of clock stages of the circuit is necessary.
Accordingly, the increase of the capacity of the memory device and the increase of the number of fail memory circuits become a cause of the increase of the fail data processing time. In view of the foregoing problems, the present invention is attained, and the object of the present invention is to provide a fail memory circuit to suppress the processing time of the interleave copy to the minimum, and its interleave copy method.
SUMMARY OF THE INVENTION
In order to attain the above object, the invention according to the fist aspect of the present invention is as the following. A fail memory circuit in which the fail data which is the information of a fail memory obtained as a result of a device test, is stored in a plurality of memory units by an interleave method, the fail memory circuit is characterized in that, it has: an address generation circuit to generate an address in which the fail data is stored; a pipe line circuit to delay the address by a predetermined constant time, when the address generated by the address circuit is inputted; a selection signal generation circuit to generate a selection signal which is a binary level signal, and output it; a selector to select either one of the output of the address generation circuit or that of the pipe line circuit, according to the selection signal, and output it; a memory array comprising a plurality of memory units, in which, when the address is inputted from the selector, the fail data stored in the address of each memory array is outputted, or the inputted fail data is written into the address of each memory array; and an OR circuit in which a plurality of fail data inputted from the memory array are OR-calculated, and outputted to the memory array.
The invention according to the second aspect of the present invention is as the following. An interleave copy method of a fail memory circuit in which the fail data which is the information of a fail memory obtained as a result of a device test, is stored in a plurality of memory units by an interleave method, the interleave copy method of the fail memory circuit is characterized in that: the address in which the fail data is stored, is generated, and is supplied as the first address to the plurality of memory units; the address is delayed by a predetermined time and supplied to the plurality of memory units as the second address; a plurality of the fail data read from the plurality of memory units according to the first address are OR-calculated; and the data obtained by the OR-processing is written in the memory units according to the second address.
REFERENCES:
patent: 5808944 (1998-09-01), Yoshitake et al.
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Hoang Huan
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