Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-11-22
2003-05-27
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S133000
Reexamination Certificate
active
06571353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a semiconductor memory tester, and a method of testing semiconductor memory. This invention in particular relates to a semiconductor memory tester and a fail information obtaining or storing device for acquiring information when a memory fails, which can be used for a semiconductor memory tester.
2. Description of Related Art
FIG. 1
shows a configuration of a semiconductor memory
40
. The semiconductor memory
40
may be a DRAM (Dynamic Random Access Memory). The semiconductor memory
40
comprises a plurality of memory blocks with remedial block
140
, which will be referred to as remedial blocks
140
. In addition to the main cell area
120
, the remedial blocks
140
further comprise a reserve cell area
110
having a spare column
110
B and a spare row
110
A. The spare column
110
B has a plurality of reserve memory cells that will be used to replace failed cells in the column direction. The spare row
110
A has a plurality of reserve memory cells to be regressed to failed cells in the row direction.
FIGS.
2
(
a
),
2
(
b
) and
2
(
c
) show the replacement of the failed cells in the reserve cells of the semiconductor memory
40
. As shown in FIG.
2
(
a
), the main cell area
120
has a plurality of failed cells
102
which cannot store data correctly. The failed cells
102
shown as “x” exist in the column direction. The memory cell line having the failed cell
102
in the column direction is replaced by a line of the spare column
110
B as shown in FIG.
2
(
b
).
In this process, the fuse in an address line corresponding to a line having failed cells
102
is cut by laser. The fuses in address lines of the spare column
110
B are cut by laser so that the spare column
110
B will be selected when an address corresponding to a replaced failed line is accessed. The failed cells
102
are replaced with normal cells as shown in FIG.
2
(
c
). Following this replacement, the semiconductor memory
40
becomes a normal chip having no failed cells.
FIGS.
3
(
a
) to
3
(
d
) show another method of replacing the failed cells with the reserve cells. The main cell area
120
has a plurality of failed cells
102
in the column direction and the spare column
110
B also has one failed cell
102
as shown in FIG.
3
(
a
). If the spare column
110
B is replaced with a line having a failed cell
102
in its column direction as shown in FIG.
3
(
b
), the replaced line will have one failed cell as shown in FIG.
3
(
c
). To avoid this situation, the line having: failed cells
102
in its column direction, must be replaced with a line from the spare column
110
B having no failed cells
102
, as shown in FIG.
3
(
d
).
Regarding a semiconductor memory tester, a memory cell function test is usually conducted not only on memory cells in the main cell area
120
but also on memory cells in the reserve cell area
110
. The test result is usually stored in a memory of a fail information obtaining or storing device provided in the semiconductor memory tester. Appropriate remedial replacement is undertaken based on the test result.
FIG. 4
shows the process and analysis on failed memory cells in an analyzer and semiconductor tester. Information concerning the failed memory cells in the main cell area
120
and reserve cell area
110
is assumed to have already been tested by the tester and to have been stored in the memory of the fail information obtaining device (not shown).
The analyzer counts failed cells based on the test results in the low addresses for each block and stores the count in a RFCM (row fail count memory). The analyzer also counts failed cells in column addresses and stores it in a CFCM (column fail count memory). The total number of failed cells is also counted and is stored in a TFCM (total fail count memory). This counting process is undertaken by a SCAN operation.
The analyzer then conducts a SEARCH operation. The analyzer analyzes the memory cell lines in the main cell area
120
and reserve cell area
110
for correct replacement, based on the fail counts stored in the RFCM, CFCM and TFCM.
It takes-considerable time to count the failed cells in the above SCAN operation, as the analyzer reads all memory cells stored in the fail information obtaining device when assessing whether or not a certain memory cell is failed. The time necessary for this operation increases as the capacity of the semiconductor memory
40
increases.
To shorten the time necessary for the analysis, a fail information obtaining device
80
is known.
FIG. 5
shows the configuration of the fail information obtaining device
80
. The fail information obtaining device
80
comprises an address selector
602
, a memory controller
604
, a memory
606
, a BFM (block fail memory)
612
, an SBFM (sub block fail memory)
654
, a BFM address selector
608
and an SBFM address selector
610
. The memory
606
comprises a plurality of memory elements, each having a predetermined memory capacity.
The address selector
602
selects and outputs an AFM address corresponding to a memory cell in the semiconductor memory
40
under test, based on the address input from a pattern generator (not shown). When a fail signal indicating a memory cell in the semiconductor memory
40
is failed, is input from the logic comparator; the memory controller
604
selects a memory element in the memory
606
to store the fail information, and asserts a fail obtaining signal /STR to be low or “0”.
The memory
606
stores as the fail information the logic level H (high) or “1” input via the terminal Dn. The data “1” is stored to a slot corresponding to the AFM address input via the terminal An, when the fail obtaining signal /STR is “L” or low. The fail obtaining signal /STR is input from the memory controller
604
via the terminal /CS.
The BFM address selector
608
selects an address of the remedial block
140
to which the memory cell indicated by the AFM address belongs. This selection is made based on the AFM address input from the address selector
602
. The BFM
612
stores as the fail information, the logic H or “1”, input via the terminal Dn. The data is stored in a slot corresponding to an address input from the BFM address selector
608
via the terminal An. This occurs when the fail obtaining signal /STR is L, input from the memory controller
604
via the terminal /CS
The SBFM address selector
610
selects an address of a sub block of the remedial block
140
to which the memory cell indicated by the AFM address belongs This selection is made based on the AFM address input from the address selector
602
. The SBFM
614
stores as the fail information the logic signal H or “1”, input via the terminal Dn. The data “1” is stored in a slot corresponding to an address input from the SBFM address selector
610
via the terminal An. This occurs when the fail obtaining signal /STR input from the memory controller
604
via the terminal /CS is “0”. There are two different ways for the SBFM address selector
610
to select the address. The SBFM
614
writes the information in a different way for each of the two different methods.
FIG. 6
shows one example of a failed memory cell in the remedial block
140
. The remedial block
140
has a plurality of failed cells
102
both in the spare column
110
B and spare row
110
A.
FIGS.
7
(
a
) and
7
(
b
) show a conventional way for the SBFM
614
to obtain the fail information of the remedial block
140
shown in
FIG. 6
In FIG.
7
(
a
), the fail information concerning the spare column
110
B and spare row
110
A is stored independently of the fail information of the sub block of the main cell area
120
. Conversely, in FIG.
7
(
b
), the fail information concerning the spare column
110
B and spare row
110
A is stored in the same area as the fail information of the sub blocks of the main cell area
120
.
In the above fail information obtaining device
80
, the time necessary for the analysis of the semiconductor memory
40
can be reduced by using the memory
606
, BFM
612
and SBFM
614
. In this de
Advantest Corporation
Iqbal Nadeem
Rosenthal & Osha L.L.P.
LandOfFree
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