Face-to-face multi-chip package

Details Face-to-face multi-chip package Face-to-face multi-chip package

1999-02-01

2001-05-29

Cuchlinski, Jr., William A. (Department: 3661)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C361S707000, C361S708000, C361S709000, C257S723000, C257S777000, C257S778000

Reexamination Certificate

active

06239366

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor packaging structure, and more particularly, to a face-to face multi-chip package.
2. Description of the Related Art
As the technology of semiconductor fabrication grows more and more advanced, the relevant techniques have to be further developed to coordinate the requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique is used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage. The third stage is the packaging process. It is now a leading trend for fabricating a device or an electronic product with a thin, light, and small dimension, that is, with a higher integration for semiconductor devices. In terms of packages, many techniques such as chip scale package, multi-chip module (MCM) have been developed to obtain a high integration. The development of the fabrication technique with a line width of 0.18 &mgr;m has evoked a great interest and intensive research to further decrease the package volume. It is thus one of the very important package techniques to arrange more than one chip into a single package. In a multi-chip package, chips of processor, memory, including dynamic random access memory (DRAM) and flash memory, and logic circuit can be packed together in a single package to reduce the fabrication cost and the packaging volume. Furthermore, the signal transmission path is shortened to enhance the efficiency. The multi-chip IC packaging technology may also be applied to a multi-chip system with variable functions and operation frequencies, for example,
1. A system comprises memory chips, microprocessors, resistors, capacitors, and inductors.
2. A system comprises memory chips (DRAM), logic circuit chips, and memory chips (Flash memory),
3. A system comprises analog chips, logic circuit chips, memory chips (including DRAM, SRAM, Flash memory), resistor, capacitor, and inductor.
In
FIG. 1
, a conventional multi-chip module is shown. A multi-level printed circuit board (PCB) is typically applied as a substrate of the to the carrier of a multi-chip module. More than one chip
12
are adhered on the substrate
10
by insulation glue
14
. The bonding pads on the chip
12
are electrically connected to the terminals on the substrate
10
by conductive wires
16
. In addition to wire bonding, the connection between the chip
12
and the substrate
10
can also be established by flip chip or controlled collapse chip connection (C
4
) with the formation of a bump. A resin
18
is used to seal the chip
12
, and the electrical connection between the whole package and a printed circuit board can be achieved by ball grid array (BGA) which use solder balls
20
to connect the terminals on the printed circuit board. The drawback of this conventional multi-chip module is that a large surface is occupied since chips are packaged on the same side of surface. Therefore, the surface area of the package is large, and the signal path between chips is long. In addition, though the volume of the package can be reduced by using flip chip technique to achieve the connection between the chip and the carrier, the connection between chips still has to be achieved by the technique of printed circuits on the substrate
10
. Therefore, it is not possible to effectively reduce signal transmission path and to shrink the volume or surface area at once. A low yield and a high cost are thus experienced in the prior art.
To further shrink the volume of package, a face to face multi-chip package is disclosed in U.S. Pat. No. 5,331,235. In
FIG. 2
, this multi-chip package comprises two chips
30
and
32
disposed face to face by way of tape automatic bonding (TAB).
FIG. 2
illustrates inner lead bonding (ILB), whereby two chips
30
,
32
having bumps
34
,
36
are electrically connected to the film carrier
38
.
FIG. 2
, further illustrates outer lead bonding (OLB), whereby the chips
30
,
32
are connected to a lead frame
40
. A solder ball
42
is formed between the chips
30
,
32
. The chips
30
,
32
, the film carrier
38
and the lead frame
40
are then molded with resin
44
. This multi-chip package uses tape automatic bonding technique. The electrical connection between chips and printed circuit board is achieved by the installation of a lead frame or other carriers. The signal transmission path is lengthened. In addition, a film carrier is used to achieve the connection between chips, the layout of metal pad on the chips is formed by a line layout or a peripheral layout. Thus, the manners of line layout or peripheral layout can not meet the integration requirement for semiconductors with greatly increased number of input/output (I/O) nodes due to further higher integration.
SUMMARY OF THE INVENTION
The invention provides a face-to-face multi-chip package with a reduced thickness and surface area. More than one chip can be packaged on one carrier.
It is another object of the invention to provide a face-to-face multi-chip package. The multi-chip chip scale package has a shortened signal transmission path to enhance the performance of the chips.
Bonding pads are allocated on the chip with as an area array to increase the integration of the package. In addition, the rear sides of chips are bared, so that the heat dissipation is enhanced.
To achieve the above-mentioned objects and advantages, a face-to-face multi-chip package is provided. A flip-chip technique is employed. More than one chip are disposed face-to-face and electrically connected via bumps.
In another embodiment of the invention, an anisotropic conductive pasted is filled between the chips to replace the conventional filled material of epoxy to fix the chips. The anisotropic conductive pasted material usually performs like an insulating material except being pressed. Thereby, the anisotropic conductive pasted material can improve the electrical connection at the connecting points, as the chips are pressed to each other for connection. A flip chip technique is used, so that the pads can be distributed on the pads in an area array. Therefore, the integration is enhanced. A heat dissipation apparatus can be further installed on the other side of the chips to improve the performance of heat dissipation.
In addition, the face-to-face multi-chip package in the invention can use lead frame, film carrier, printed circuit board, or glass as a carrier. The package is applicable in many different types of packages such as ball grid array package, chips on board (COB), chips on glass (COG), and multi-chip chip scale package (MCCSP). An improved packaging quality and an enhanced reliability are obtained.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
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patent: 5734199 (1998-03-01), Kawakita et al.
patent: 5757080 (1998-05-01), Sota
patent: 5773896 (1998-06-01), Fujimoto et al.
patent: 5777345 (1998-07-01), Loder et al.
patent: 5790384 (1998-08-01), Ahmad et al.
patent: 5804882 (1998-09-01), Tsukagishi et al.
patent: 5872700 (1999-02-01), Collander
patent: 5894165 (1999-04-01), Ma et al.
patent: 5936305 (1999-10-01), Akram

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