Fabrication process of semiconductor integrated circuit device

Details Fabrication process of semiconductor integrated circuit device Fabrication process of semiconductor integrated circuit device

2000-09-26

2002-06-11

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S624000

Reexamination Certificate

active

06403459

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a technique for fabrication of a semiconductor integrated circuit device and the semiconductor integrated circuit device fabricated by using this technique. Particularly, the present invention pertains to a technique which is effective when applied to a semiconductor integrated circuit device having a metal interconnection, which has, as a main conductive film, copper or the like, and is formed by depositing a thin copper film in a groove and removing a portion of the thin copper film from a region outside the groove by the CMP (Chemical Mechanical Polishing) method.
In the conventional semiconductor integrated circuit device, an interconnection film was formed, for example, by forming a thin film of a high-melting-point metal, such as aluminum (Al) alloy or tungsten (W), over an insulating film, forming a resist pattern having the same shape as that of the interconnection pattern over a thin film for interconnection by photolithography and then forming the interconnection pattern by dry etching using the resist pattern as a mask.
The conventional process using an Al alloy or the like is, however-accompanied with a drawback in that, attendant on the miniaturization of the interconnection, the interconnection resistance shows a marked increase, which inevitably increases an interconnection delay, resulting in a deterioration in the performance of the semiconductor integrated circuit device. Such a drawback has led to a serious problem particularly in a high-performance logic LSI and represents a factor for disturbing its performance.
The IBM J. Res. Develop., 39(4), the July issue, 419-435(1995) or 1996 Symposium on VLSI Technology Digest of Technical Papers, pp48-49, describes a process (so-called damascene method) for forming an interconnection pattern in a groove, which comprises embedding an interconnection metal, which has copper (Cu) as a main conductive film, formed in an insulating film and then removing an unnecessary portion of the metal outside the groove by the CMP (chemical machine polishing) method.
The Japanese Patent Application Laid-Open No. HEI 7-297183, describes a technique which comprises forming an interconnection groove on an insulating film formed over a semiconductor substrate, overlaying another insulating film, overlaying a conductive interconnection film, forming a planarizing film made of SOG (Spin On Glass) so as to embed the interconnection groove with the planarizing film, and polishing the planarizing film. The conductive interconnection film, thereby leaving an interconnection made of the conductive interconnection film in the interconnection groove.
SUMMARY OF THE INVENTION
As a result of investigation on the above process which comprises embedding an interconnection metal having copper (Cu) or the like as a main conductor film in a groove formed in an insulating film and then removing an unnecessary portion of the metal outside the groove by the CMP (Chemical Mechanical Polishing) method, however, the present inventors found that the process is accompanied with the following problems. The problems investigated by the present inventors will be described with reference to FIG.
73
(
a
) to
73
(
c
), in which FIG.
73
(
a
) is a plain view, FIG.
73
(
b
) is a cross-sectional view taken along a line b—b of FIG. FIG.
73
(
a
) and FIG.
73
(
c
) is a cross-sectional view taken along a line c—c of FIG. FIG.
73
(
a
), and wherein only a problematic interconnection film is illustrated while other members are omitted.
For the formation of an interconnection
202
over an insulating film
201
, first, an insulating film
203
for interconnection formation is deposited over the insulating film
201
and an interconnection groove
204
is formed in the insulating film
203
. As the insulating film
203
, a silicon oxide film is usually employed. Second, a metal film (for example, copper (Cu)) which is to constitute the interconnection
202
is deposited over the insulating film
203
so as to embed the interconnection groove
204
, followed by the removal of a portion of the metal film over the insulating film
203
outside the interconnection groove
204
by polishing, whereby only the metal film inside the interconnection groove
204
remains and the interconnection
202
is formed. When the silicon oxide film used as the insulating film
203
is compared with the metal (ex. copper) which constitutes the interconnection film
202
, the polishing rate of the latter by the CMP method is generally greater. Such a difference in the polishing rate inevitably results in a concave portion
205
being formed on the surface of the interconnection
202
. This concave portion
205
is known as dishing (concave). In addition, scratches appear on the surface of the insulating film
203
as a result of polishing by the CMP method.
If an insulating film
206
is formed over such a concave portion
205
or a scratch without removing it from the surface of the insulating film
203
, another concave portion
205
or a further concave portion attributable to the scratch also appears on the surface of the insulating film
206
. If a plug
207
is formed in the insulating film
206
by the CMP method without removing the concave portion, the conductive substance
208
which constitutes the plug
207
remains in the concave portion on the surface of the insulating film
206
. Described more specifically, the plug
207
is formed by embedding a metal film, which is to constitute the plug
207
, inside a connecting hole opened in the insulating film
206
and, at the same time, depositing the metal film over the insulating film
206
; and then removing the metal film over the insulating film
206
by the CMP method to leave only a portion-of the metal film inside of the connecting hole. If a concave portion (including a concave portion attributable to a scratch) exists on the surface of the insulating film
206
, the conductive substance
208
, which is a residue of the metal film, also remains inside of the concave portion. Incidentally, there is a possibility of that the metal film will remain in the concave portion attributable to a scratch, but this is not illustrated.
Such a residue of the conductive substance
208
is not intended and is undesired, because when an insulating film
209
is formed over the plug
207
and an interconnection
210
is formed in the interconnection groove of the insulating film
209
, two adjacent interconnections
210
, which are to be electrically disconnected, form a short circuit owing to the existence of the conductive substance
208
, leading to a short-circuit problem in the semiconductor integrated circuit device.
Such a short circuit problem occurs similarly when an interconnection is formed by the so-called dual damascene method without using the plug
207
.
An object of the present invention is to provide a technique for improving surface flatness of an interlayer insulating film over a first metal interconnection formed by the CMP method.
Another object of the present invention is to suppress a short circuit of a second metal interconnection over a first metal interconnection formed by the CMP method, thereby improving the yield and reliability of the semiconductor integrated circuit device.
The above-described and other objects and novel features of the present invention will be apparent from the description herein and the drawings attached.
Among the aspects of the inventions disclosed herein, representative ones will next be summarized simply.
(1) In one aspect of the present invention, there is provided a semiconductor integrated circuit device which comprises a semiconductor device formed over a principal surface of a semiconductor substrate; a first insulating film which is formed over the semiconductor device and has a first conductive member, which has been formed by the CMP method, embedded in each of first concave portions formed in the first insulating film; and a second insulating film which is formed over the first insulating film and has a second conductive me

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