Fabrication process of semiconductor device

Details Fabrication process of semiconductor device Fabrication process of semiconductor device

2000-04-20

2002-05-21

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S584000, C438S621000, C438S625000, C438S627000, C438S648000, C438S678000, C438S680000, C438S683000

Reexamination Certificate

active

06391774

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a fabrication process of a semiconductor device. More particularly, the invention relates to a fabrication process of a semiconductor device which has wiring and groove wiring of copper (Cu) formed on a semiconductor substrate.
2. Description of the Related Art
In the recent years, Cu is attracting attention as a material for forming wiring of a large scale integrated circuit (LSI) for increasing package density and speeding up. Furthermore, when Cu is used for the LSI wiring, since formation of wiring by dry etching is difficult. Therefore, a current major trend is a damascene wiring, in which a wiring groove is formed preliminarily, Cu is buried therein and polishing is performed for leaving Cu in the wiring groove. However, associating with increasing of package density of the LSI, the wiring groove is progressively narrowed to cause difficulty in burying Cu within the wiring groove by way of sputtering.
As a measure for this, an electrolytic plating method has been currently employed. Such electrolytic plating method has been disclosed in Japanese Unexamined Patent Publication No. Showa 63-164241. The disclosed technology uses the electrolytic plating method for burying Cu in a contact hole. This type of device have also been disclosed in Japanese Unexamined Patent Publication No. Heisei 3-68190 and Japanese Unexamined Patent Publication No. Heisei 3-263896, for example.
However, the Cu film deposited by the electrolytic plating method had small grain, and the Cu groove wiring formed using the Cu film formed by electrolytic plating has low electromigration resistance. Here, electromigration is a phenomenon to cause local thickening or thinning of the wiring due to motion of atom during application of electric power. In order to improve electromigration resistance, it becomes necessary to make the grain size greater so as not to leave grain boundary in the wiring.
On the other hand, using an RF-DC coupling bias sputtering method, a DC bias higher than or equal to a certain value is applied to the substrate deposit the Cu film with striking a sputter growth surface by argon ion. At this time, a film of (111) orientation as the highest density surface is deposited to reduce a distance between Cu atoms to accumulate stress energy within the film. When heat treatment is performed subsequently, the stress energy is discharged to change crystal orientation of the Cu film from Cu(111) to thermally stable Cu(200). At the same time, giant grain growth greater than or equal to several hundreds &mgr;m is caused in the Cu film. This has been reported in “Electrical Properties of Giant-Grain Copper Thin Film Formed by a Low Kinetic Energy Particle Process”, J. Eelectrochem. Soc., Vol. 139, March, 1992, pp. 922-927 (hereinafter referred to as publication 1).
On the other hand, after depositing Cu by normal sputtering, Cu is deposited in two stages with applying the DC bias higher than or equal to the certain value. By subsequently performing heat treatment, a stress energy is transferred from the layer deposited with applying the DC bias to the layer deposited by normal sputtering to cause variation of the crystal orientation and grain growth in the entire film similarly to the foregoing publication 1. This has been reported in “Formation of giant-grain copper interconnects by a low-energy ion bombarment process for high speed ULSIs”, Journal of Materials Chemistry and Physics, 99(1995), pp. 1-10 (hereinafter referred to as publication 2).
As set forth above, by sputter deposition with irradiating ion beam, Cu film having giant grain of several 100 &mgr;m can be formed. However, both sputtering methods are disadvantageous in comparison with the plating method in terms of burying in the wiring groove. Namely, even if the either sputtering method is employed, it is difficult to bury Cu within the wiring groove.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a fabrication process of a semiconductor device which can bury Cu within a wiring groove and a grain is large.
According to one aspect of the present invention, a fabrication process of a semiconductor device, in which wiring is formed on the semiconductor substrate, comprises:
a first step of depositing a first conductive film on the substrate via an insulation film;
a second step, subsequent to the first step, of depositing a second conductive film having film thickness thicker than the film thickness of the first conductive film, on the first conductive film;
a third step following the second step, of performing heat treatment at least for the first and second conductive films; and
a fourth step following the third step, of forming wiring by shaping the conductive films after the heat treatment.
In the construction set forth above, a groove for burying wiring is formed in the insulation film. In the alternative, a via hole is formed in the insulation film. In the preferred process, the first step comprises:
a first sub-step of depositing a first sub-layer by sputtering; and
a second sub-step following the first sub-step of depositing a second sub-layer on the first sub-layer by an electrolytic plating,
for forming the first conductive film with the first sub-layer and the second sub-layer.
The first conductive film may be deposited in the first step by plasma CVD.
In the preferred process, the second step comprises:
a first sub-step of sputtering and reducing oxide on a surface of the first conductive film; and
a second sub-step following the first sub-step, of applying bias to the semiconductor substrate and irradiating argon gas onto a growth surface within a sputtering chamber. The third step may be performed a heat treatment at a given temperature and a given period under argon atmosphere. The fourth step is performed for forming a groove wiring by removing a conductive film other than wiring portion by a mechanical chemical polishing.
Preferably, the conductive film is formed by copper.


REFERENCES:
patent: 6207558 (2001-03-01), Singhvi et al.
patent: 3-68190 (1991-03-01), None
patent: 3-263896 (1991-11-01), None
patent: 7-115073 (1995-05-01), None
patent: 7-201853 (1995-08-01), None
patent: 9-306912 (1997-11-01), None
patent: 10-4139 (1998-01-01), None
Takahisa Nitta, “Electrical Properties of Giant-Grain Copper Thin Films Formed by a Low Kinetic Energy Particle Process”, Mar. 1992, pp. 922-927.
Takewaki et al., “Materials Chemistry and Physics”, Mar. 1995, pp. 182-191.
Japanese Office Action dated Dec. 4, 2001 with partial English Translation.
T. Takewaki et al. “Formation of giant-grain copper interconnects by a low-energy ion bombardment process for high-speed ULSIs”, Materials Chemistry and Physics 4 (1995) pp. 182-191.

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