Fabrication process of semiconductor device

Details Fabrication process of semiconductor device Fabrication process of semiconductor device

1997-05-28

1998-06-30

Niebling, John

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438624, 438633, H01L 21302, H01L 214763

Patent

active

057733651

ABSTRACT:
An interlayer insulation layer is formed on a semiconductor substrate and a groove of a wiring shape is formed in the interlayer insulation layer. Then, the groove is buried with conductor. A part of the conductor is covered with a mask material, and a part of the conductor not covered with the mask is etched to form a recess. Thus, a first wiring is defined at a part of the conductor under the recess, and a columnar projection to be a connecting portion of wirings is defined at a side of the recess on the first wiring. An insulation layer is buried in the recess except for the upper surface of the columnar projection. A second wiring covering at least a part of the exposed upper surface of the columnar projection is formed.

REFERENCES:
patent: 4617723 (1986-10-01), Mukai
patent: 5055426 (1991-10-01), Manning
patent: 5210053 (1993-05-01), Yamagata
patent: 5358903 (1994-10-01), Kim
patent: 5453154 (1995-09-01), Thomas et al.
patent: 5462893 (1995-10-01), Matsuoka et al.
patent: 5602053 (1997-02-01), Zheng et al.
patent: 5637534 (1997-06-01), Takeyasu et al.

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