Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1998-05-14
2000-09-26
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438149, 438287, H01L 2100, H01L 21336
Patent
active
061241547
DESCRIPTION:
BRIEF SUMMARY
FIELD OF TECHNOLOGY
The present invention relates to the fabrication process of thin film transistors (abbreviated as TFT below). Further, in detail, the present invention relates to optimized technology for each thin film which comprises the thin film transistor.
BACKGROUND TECHNOLOGY
In thin film transistors (TFT) that are used in applications such as active elements in liquid crystal displays, a top gate structure in which a gate insulator layer and gate electrode are formed on the top side of the channel region is often used. In the fabrication process for this type of TFT structure, after substrate 10A is prepared as shown in FIG. 25(A), underlevel protection layer 11A is formed on the surface of substrate 10A as shown in FIG. 25(B), after which semiconductor layer 12A consisting of an intrinsic amorphous silicon film is formed over the entire surface of substrate 10A. Next, semiconductor layer 12A is crystallized through laser annealing as shown in FIG. 25(C). Next, as shown in FIG. 26(A), resist mask 22A with a fixed mask pattern is formed; and semiconductor layer 12A is patterned using photolithography. Next, as shown in FIG. 26(B), gate insulator layer 13A consisting of a silicon oxide film is formed on the surface of semiconductor layer 12A by means of CVD. Next, as shown in FIG. 26(C), after conducting layer 21A consisting of a tantalum or other thin film is formed over the entire surface of substrate 10A by a means such as sputtering; gate electrode 15A is formed by patterning conducting layer 21A using photolithography as is shown in FIG. 26(D). Next, impurity ions are introduced into semiconductor layer 12A while using gate electrode 15A as a mask. As a result, source and drain regions 16A which are self-aligned with respect to gate electrode 15A are formed in semiconductor layer 12A; and the region of semiconductor layer 12A in which impurities ions were not introduced forms channel region 17A. Next, as shown in FIG. 26(E), after interlevel insulation film 18A consisting of a silicon oxide film is formed, source and drain electrodes 20A which form conducting junctions to source and drain regions 16A through contact holes 19A are formed. In this manner, TFT 30A is formed on the surface of substrate 10A. In this type of fabrication process, in the prior art, substrate 10A is exposed to atmosphere after a single process step is completed.
In the fabrication process of the prior art, however, when substrate 10A is exposed to atmosphere following completion of the annealing treatment of semiconductor layer 12A, the surface of crystallized semiconductor layer 12A can be oxidized through reactions to gaseous species, contaminated by hydrocarbons from the resist, for example, or contaminated by other impurities. In such a case, if gate insulator layer 13A is formed on the surface of semiconductor layer 12A that has been oxidized or contaminated, there will be a problem because the condition of the interface between channel region 17A and gate insulator layer 13A will deteriorate; and the electrical characteristics, such as the on current and the threshold voltage, of TFT 30A will worsen. Also, if, prior to crystallization by laser irradiation or other means, a natural oxide forms on semiconductor layer 12A as a result of the exposure of substrate 10A to atmosphere, there will be a problem because oxygen atoms will be incorporated into semiconductor layer 12A, the electrical conductivity of semiconductor layer 12A will vary widely, and the electrical characteristics of TFT 30A such as on current will worsen.
As a method to avoid such problems, a TFT fabrication process in which the semiconductor layer is not exposed to atmosphere is presented in Japanese Unexamined Patent Application Heisei 7-99321. In the process described as Example 2 in the aforementioned document, after substrate 10B is prepared as shown in FIG. 27(A), a phosphorous-doped semiconductor layer is formed on the surface. The semiconductor layer is patterned to form semiconductor layer islands 25B as shown in FIG. 27(B). Next, sub
REFERENCES:
patent: 5811328 (1998-09-01), Zhang et al.
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Mitra et al., "Low-Temperature Polysilicon TFT with Gate Oxide Grown by High-Pressrue Oxidation", IEEE Electron Device Letters, vol. 12, No. 7, pp. 390-392.
Kato et al., "Damageless H2O/SiH4 Plasma-CVD for gate SiO2", VLSI Technology Digest of Technical Papers: 1993 syposium, pp. 153-4.
Jelenkovic et al., "Thin Film Transistors based on sputtered silicon and gate oxide films", Electron Devices Meeting, 1996, pp. 41-44.
Campo et al., "Influence of Rapid Thermal and Low Temperature Processing on the Electrical Properties of Polysilicon Thin Film Transistors", IEEE Transactions on Semiconductor Manufacturing, pp. 298-303, Aug. 1995.
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Bowers Charles
Pert Evan
Seiko Epson Corporation
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