Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-07-21
2002-09-03
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000
Reexamination Certificate
active
06444507
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to the fabrication process of thin film transistors (abbreviated as TFT below). Further, in detail, the present invention relates to optimized technology for each thin film which comprises the thin film transistor.
2. Description of Related Art
In thin film transistors (TFT) that are used in applications such as active elements in liquid crystal displays, a top gate structure in which a gate insulator layer and gate electrode are formed on the top side of the channel region is often used. In the fabrication process for this type of TFT structure, after substrate
10
A is prepared as shown in FIG.
25
(A), underlevel protection layer
11
A is formed on the surface of substrate
10
A as shown in FIG.
25
(B), after which semiconductor layer
12
A consisting of an intrinsic amorphous silicon film is formed over the entire surface of substrate
10
A. Next, semiconductor layer
12
A is crystallized through laser annealing as shown in FIG.
25
(C). Next, as shown in FIG.
26
(A), resist mask
22
A with a fixed mask pattern is formed; and semiconductor layer
12
A is patterned using photolithography. Next, as shown in FIG.
26
(B), gate insulator layer
13
A consisting of a silicon oxide film is formed on the surface of semiconductor layer
12
A by means of CVD. Next, as shown in FIG.
26
(C), after conducting layer
21
A consisting of a tantalum or other thin film is formed over the entire surface of substrate
10
A by a means such as sputtering; gate electrode
15
A is formed by patterning conducting layer
21
A using photolithography as is shown in FIG.
26
(D). Next, impurity ions are introduced into semiconductor layer
12
A while using gate electrode
15
A as a mask. As a result, source and drain regions
16
A which are self-aligned with respect to gate electrode
15
A are formed in semiconductor layer
12
A; and the region of semiconductor layer
12
A in which impurities ions were not introduced forms channel region
17
A. Next, as shown in FIG.
26
(E), after interlevel insulation film
18
A consisting of a silicon oxide film is formed, source and drain electrodes
20
A which form conducting junctions to source and drain regions
16
A through contact holes
19
A are formed. In this manner, TFT
30
A is formed on the surface of substrate
10
A. In this type of fabrication process, in the prior art, substrate
10
A is exposed to atmosphere after a single process step is completed.
In the fabrication process of the prior art, however, when substrate
10
A is exposed to atmosphere following completion of the annealing treatment of semiconductor layer
12
A, the surface of crystallized semiconductor layer
12
A can be oxidized through reactions to gaseous species, contaminated by hydrocarbons from the resist, for example, or contaminated by other impurities. In such a case, if gate insulator layer
13
A is formed on the surface of semiconductor layer
12
A that has been oxidized or contaminated, there will be a problem because the condition of the interface between channel region
17
A and gate insulator layer
13
A will deteriorate; and the electrical characteristics, such as the on current and the threshold voltage, of TFT
30
A will worsen. Also, if, prior to crystallization by laser irradiation or other means, a natural oxide forms on semiconductor layer
12
A as a result of the exposure of substrate
12
A to atmosphere, there will be a problem because oxygen atoms will be incorporated into semiconductor layer
10
A, the electrical conductivity of semiconductor layer
10
A will vary widely, and the electrical characteristics of TFT
30
A such as on current will worsen.
As a method to avoid such problems, a TFT fabrication process in which the semiconductor layer is not exposed to atmosphere is presented in Japanese Unexamined Patent Application Heisei 7-99321. In the process described as Example 2 in the aforementioned document, after substrate
10
B is prepared as shown in FIG.
27
(A), a phosphorous-doped semiconductor layer is formed on the surface. The semiconductor layer is patterned to form semiconductor layer islands
25
B as shown in FIG.
27
(B). Next, substrate
10
B is inserted into a TFT fabrication unit and semiconductor layer
12
B consisting of an amorphous silicon film is formed in vacuum using CVD as shown in FIG.
27
(C). Next, as shown in FIG.
27
(D), substrate
10
B is laser annealed under vacuum. As a result, except for the region which becomes channel
17
B, semiconductor layer
12
B is phosphorous doped and source and drain regions
16
B are formed. Next, as shown in FIG.
27
(E), gate insulator layer
13
B is formed on substrate
10
B in vacuum using CVD; and substrate
10
B is then removed from the TFT processing apparatus. At this point, the surface of semiconductor layer
12
B is already covered by gate insulator layer
13
B.
After this, as shown in FIG.
27
(F), following photolithographic patterning of gate insulator layer
13
B and semiconductor layer
12
B, contact holes
19
B are formed as shown in FIG.
28
(A). After conducting layer
21
B consisting of aluminum or other material is formed over the entire surface, gate electrode
15
B is formed through further photolithography as shown in FIG.
28
(B). Next, following formation of interlevel insulation film
18
B as shown in FIG.
28
(C), contact holes
26
B are formed as shown in FIG.
28
(D). Following formation of a conducting layer such as aluminum over the entire surface, the conducting layer is patterned by photolithography as shown in FIG.
28
(E), and source and drain electrodes
20
B are formed.
In this method, however, semiconductor layer
12
B and gate insulator layer
13
B are patterned simultaneously as shown in FIG.
27
(F). As a result, as shown in FIGS.
28
(A) and (B), when gate electrode
15
B is formed during the next process steps through the patterning of conducting layer
21
B which has been formed over the entire surface of substrate
10
B, conducting layer
21
B remains on the side walls of source and drain regions
16
B. This leads to frequent occurrences of shorting between the source and drain regions, or between the source-gate and drain-gate regions. Further, there is also a problem with shorting to other TFTs on substrate
10
B. In other words, in the fabrication process of the prior art, there is a problem with noticeably low yields of TFTs.
Moreover, in the prior art, in the process step shown in FIG.
27
(D), silicon oxide species formed on top of semiconductor layer
25
B or impurities from the resist or other sources may be incorporated into the semiconductor layer (mostly into source and drain regions) during laser melting. These impurities produce defects in the semiconductor layer and give rise to increases in off leakage current and threshold voltage shifts. Additionally, the surface of substrate
10
B prior to the formation of semiconductor layer
12
B is contaminated by the photolithography step to produce the source and drain. These impurities are intermixed in channel region
17
B during crystallization causing a decrease in semiconductor layer film quality. Accordingly, in this prior art, since not only is the on current limited by impurities from the substrate surface, but the off current also increases as a result of oxygen (silicon oxide species) and contamination in the source and drain regions, it is not possible to produce high quality thin film semiconductor devices with large on-off current ratios.
Further, in this prior art, because gate insulator layer
13
B formed by CVD is used in the as-deposited condition, the gate insulator layer film quality is not good and is known to lead to problems such as low gate-source breakdown voltages. As a result, there are problems both with the TFT electrical characteristics being poor as well as the yield and reliability being low. Additionally, a further problem exists since, as shown in FIG.
27
(D), only laser annealing is done for semiconductor layer
12
B which was formed by CVD. The result is retention of large stresse
Christianson Keith
Oliff & Berridg,e PLC
Seiko Epson Corporation
Smoot Stephen W.
LandOfFree
Fabrication process for thin film transistors in a display... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication process for thin film transistors in a display..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication process for thin film transistors in a display... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2907333