Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-08-17
2001-11-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S250000, C438S381000, C438S148000
Reexamination Certificate
active
06313003
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a capacitor for mixed-mode applications that has low gate resistance.
(2) Description of the Prior Art
The manufacturing of semiconductor devices applies a number of different but interacting disciplines that collectively create high performance semiconductor devices. The majority of these semiconductor devices have as function the processing of digital information which is characterized by zero and one conditions, typically created by on-off conditions of switching transistors. In addition, hybrid functions can be provided that address not only the processing of digital signals but also address the processing of analog signals, either as a function that is provided by one analog semiconductor device or in collaboration with digital devices. Device performance improvements have been sought and established by continuously decreasing device dimensions thereby concurrently increasing device packaging density. This poses problems for a number of the typical analog components such as capacitors and inductors that have physical dimensions that do not lend themselves to ready integration into a highly miniaturized, sub-micron device environment.
The mixing of functions and processing capabilities results in a mixing of components that coexist within one semiconductor device. It is therefore not uncommon to see resistors and capacitors that form part of a semiconductor device which does not negate the fact that the vast majority of device components is made up of transistors, gate electrodes and a variety of switching components that address logic processing functions. Capacitors can for instance form a basic component of analog circuits that are used for analog applications such as switched capacitor filters. Capacitors are also widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor. Mixed mode applications as part of logic processing is expected to find increased application with an emphasis on high frequency applications. Continued reduction in device dimensions has further placed greater emphasis on using copper as an interconnect material, the limitation that this approach experiences however is that the technology of creating capacitive components in a copper interconnect environment is as yet in its infancy, especially where this interconnect environment makes use of the copper damascene process. One process has recently been explored that uses TaN as the material of choice for the creation of the capacitor, this approach however includes the application of an oxide etch stop on the applied TaN material resulting in problems of planarization and etching control and accuracy.
The DRAM technology is widely used for data storage where one transistor and one capacitor form one DRAM cell. For the capacitor a stacked capacitor is frequently used since this structure has good data storage performance characteristics combined with low surface space requirements. To fabricate a DRAM device, a modified CMOS process is typically used. One other application in which the CMOS structure has been successfully applied is in the creation of image sensors.
With the conventional damascene process, a metal via plug is first formed in a surface, typically the surface of a semi-conductor substrate. A layer of dielectric (for instance SiO
2
) is deposited over the surface (using for instance PECVD technology); trenches (for metal lines) are formed in the dielectric (using for instance RIE technology). Metal is deposited to fill the trenches; the excess metal on the surface is removed. A planar structure of interconnect lines with metal inlays in the (intralevel) dielectric is achieved in this manner.
An extension of the damascene process is the dual damascene process whereby an insulating or dielectric material, such as silicon oxide, is patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings are also formed. One of the dual damascene approaches uses a dielectric layer that is formed by three consecutive depositions whereby the central layer functions as an etch stop layer. This etch stop layer can be SiN, the top and bottom layer of this three layer configuration can be SiO
2
. This triple layer dielectric allows first forming the vias by resist patterning the vias and etching through the three layers of dielectric. The conductive pattern can then be formed in the top layer of dielectric whereby the central layer of SiN forms the stop layer for the etch of the conducting pattern. Another approach, still using the three-layer dielectric formed on the substrate surface, is to first form the pattern for the conducting lines in the top layer of the dielectric whereby the SiN layer again serves as etch stop. The vias can then be formed by aligning the via pattern with the pattern of the conducting lines and patterning and etching the vias through the etch stop layer of SiN and the first layer of dielectric. Yet another approach is to deposit the three layer dielectric in two steps, first depositing the first layer of SiO
2
and the etch stop layer of SiN. At this point the via pattern can be exposed and etched. The top layer of SiO
2
dielectric is then deposited; the conducting lines are now patterned and etched. The SiN layer will stop the etching except where the via openings have already been etched.
Low resistivity metals such as aluminum and copper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. Typical examples of fine line interconnect metals include Al
x
Cu
y
, ternary alloys and other similar low resistivity metal-based alloys. Emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacturing has led to reliability problems including inadequate isolation, electromigration, and planarization. Damascene processes using metal fill vias and lines followed by chemical mechanical polishing (CMP) with various Al, Cu and Cu-based alloys are a key element of future wiring technologies for very large-scale system integration (VLSI). A key problem is filling high aspect ratio vias and lines without voids or seams, and creating homogeneous structures.
As already stated, copper is at this time explored as an alternate metal to be used as an interconnect metal. Copper has so far not found wide application as an interconnect metal, this despite its relatively low cost, low resistivity, which electromigration resistance and stress voiding resistance. Copper also suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is frequently use as a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a which dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between
Ackerman Stephen B.
Bowers Charles
Huynh Yennhu B
Saile George O.
Taiwan Semiconductor Manufacturing Company
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