Fabrication process for a semiconductor device with...

Details Fabrication process for a semiconductor device with... Fabrication process for a semiconductor device with...

2001-06-28

2002-11-19

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C257S760000, C438S622000, C438S623000, C438S624000

Reexamination Certificate

active

06483193

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and fabrication process thereof, particularly to a miniaturized interconnect structure and fabrication process thereof.
2. Description of the Related Art
With a tendency to miniaturization of a semiconductor element, multilevel miniaturized interconnection has become indispensable for the constitution of a semiconductor device. In recent days, as an interlevel insulator for such a semiconductor device having multilevel interconnection, silicon dioxide film type insulators having a relatively small dielectric constant and stable quality have come to be used mainly in order to reduce a parasitic capacitance between upper and lower interconnect layers or within the same interconnect layers.
The miniaturization of a semiconductor element brings about reductions in the interconnect width and interconnect distance of the lower layers, but it becomes necessary to secure a certain extent of cross-sectional area for interconnection to avoid an increase in the interconnect resistance. As a result, an aspect ratio (interconnect height/ interconnect distance) between interconnect layers as well as an aspect ratio (interconnect height/interconnect width) of an interconnect layer shows an increase, which has come to bring about a marked increase in a parasitic capacitance between interconnect layers, lower a propagation rate of signals or cause crosstalk (a phenomenon that signal noises appear between adjacent interconnect layers) between interconnect layers frequently.
When a large stepped portion exists on the surface of an interlevel insulator, a fine resist pattern cannot be formed, upon formation of an upper interconnect layer, by photolithography because of a shortage in a focus margin. Even if a fine resist pattern can be formed, disconnecting portion or etching remnants of interconnect materials are generated at the stepped portion of the upper layer owing to a large step difference. The surface of an interlevel insulator is therefore required to be planarized.
With a view to overcoming the problems caused by such fine multilevel interconnection, various means of employing an interlevel insulator having a low dielectric constant have been proposed. For example, proposed is a technique described in “Semiconductor World, No. 8, 26-30(1995)” which is a monthly journal. The proposed technique will next be described with reference to accompanying drawings.
FIGS. 8 and 9
are cross-sectional views of a double-level interconnect structure for illustrating the above conventional technique in the order of fabrication steps. As illustrated in FIG.
8
(
a
), a thick insulating layer
101
is formed on the surface of a silicon substrate. Over this thick insulating layer
101
, a first barrier metal layer
102
, a first interconnect metal layer
103
and a second barrier metal layer
104
are formed by stacking them one after another. Over the second barrier metal layer
104
, a mask insulating layer
105
is formed, followed by the formation of a resist mask
101
a
by photolithography.
With the resist mask
101
a
as an etching mask, the mask insulating layer
105
is subjected to reactive ion etching (RIE), whereby hard mask layers
105
a
and
105
b
are formed. The resist mask
101
a
is then removed, followed by dry etching of the second barrier layer
104
, first interconnect metal layer
103
and first barrier metal layer
102
successively with the hard mask layers
105
a
and
105
b
as masks. In this manner, as illustrated in FIG.
8
(
b
), formed on the thick insulating layer
101
are the first barrier metal layers
102
a
and
102
b
, on which first interconnect layers
103
a
and
103
b
are formed, respectively. On the first interconnect layers
103
a
and
103
b
, second barrier metal layers
104
a
and
104
b
are formed, respectively.
As illustrated in FIG.
8
(
c
), a protective insulating layer
106
is then formed to cover the whole surface, followed by the formation of an organic SOG layer
107
.
As illustrated in FIG.
8
(
d
), the organic SOG layer
107
is then polished by chemical machanical polishing (CMP) and is planarized. Here, the protective insulating layer
106
functions as an etching stopper layer. In this manner, a first interlevel insulator composed of a protective insulating layer
106
and an organic SOG layer
107
is formed. The organic SOG layer
107
is a low-dielectric-constant insulating layer having a relative dielectric constant as low as about 3. In comparison, a silicon dioxide layer has a relative dielectric constant of about 4.
As illustrated in FIG.
9
(
a
), a second interlevel insulator
108
is formed over the first interlevel insulator, followed by the formation of a through-hole
109
, which reaches the second barrier metal layer
104
a
, in an interlevel insulator, that is, a second interlevel insulator
108
, the protective insulating layer
106
and the hard mask layer
105
a
above the first interconnect layer
103
a.
As illustrated in FIG.
9
(
b
), a metal plug
110
to be connected with the second barrier metal layer
104
a
is then filled in the through-hole and a third barrier metal layer
111
to be connected with the metal plug
110
, a second interconnect layer
112
and a fourth barrier metal layer
113
are formed successively.
In such an interconnect structure, the first interconnect layers
103
a
and
103
b
which are contiguous each other are formed on the thick insulating layer
101
with the insulating layer formed of the protective insulating layer
106
and organic SOG layer
107
therebetween. The interlevel insulator formed in the lower interconnect region has been planarized.
According to the above-described manner, an interconnect structure having a low-dielectric-constant insulating film formed between adjacent interconnect lines and having a planarized interlevel insulator can be fabricated.
In the interconnect structure of a semiconductor device according to the conventional method as described above, however, a low-dielectric-constant insulating layer is formed even in a widely-spaced region between adjacent interconnect lines. The low-dielectric-constant insulating layer has, in general, a large coefficient of thermal expansion and its strength is low, which tends to cause cracks in the interlevel insulator of the semiconductor device. Particularly, in the case of a multilevel interconnect structure, such a phenomenon occurs frequently.
According to the conventional method, a low-dielectric-constant insulating layer is formed all over the region except the interconnect lines and the side portions of interconnect lines. The low-dielectric-constant insulating layer generally has high hygroscopicity. This tendency increases with the lowering in the dielectric constant. An increase in the water content in the interlevel insulator lowers the insulation property, leading to the deterioration in the quality of the interconnect structure. Such a loss of reliability becomes more eminent in the case of a multilevel interconnect structure.
Such a loss of reliability of the interconnect structure, on the contrary, imposes a limitation on a tendency to reduce the dielectric constant of an interlevel insulator.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an interconnect structure which brings about an improvement in the reliability of a miniaturized interconnect structure, facilitates the heightening of an interconnect performance and is capable of meeting the requirements of a multilevel miniaturized interconnect layer, fabrication process thereof.
In the present invention, there is thus provided a semiconductor device wherein a plurality of interconnect lines are disposed, through an insulating layer, on a same layer above a semiconductor substrate having a semiconductor element, a first interlevel insulator is formed selectively in a narrowly-spaced region between adjacent interconnect lines, a second interlevel insulator is formed in a widely-spaced region between adjacent interconnect

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