Fabrication process for a semiconductor device

Details Fabrication process for a semiconductor device Fabrication process for a semiconductor device

2000-01-31

2002-09-10

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Gettering of substrate

C438S476000, C438S402000, C438S477000, C438S795000, C438S928000

Reexamination Certificate

active

06448157

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as DRAM (Dynamic Random Access Memory) and a fabrication process therefor. More particularly the present invention relates to a semiconductor device and a fabrication process therefor in which deterioration of an element isolation withstand voltage that is caused by a pit defect existing at a surface of a silicon substrate obtained by means of a Czochralski (Cz) method is prevented from occurring.
2. Description of the Related Art
FIG. 1
is a plan view showing a structure of a conventional DRAM, and
FIG. 2
is a sectional view taken along line B—B of FIG.
1
and
FIG. 3
is a sectional view taken along line C—C of FIG.
1
. These figures show a state of a highly integrated DRAM memory cell in which a gate electrode being a word line has been formed. A P-type silicon substrate
1
has a major surface with an orientation of (100) and a resistivity of the order of 5 &OHgr;cm. Further, this substrate
1
is a Cz silicon wafer with an orientation flat along the <110> direction. An element isolation insulating film
2
constituted of a silicon oxide film is formed by means of a LOCOS (Local Oxidation of Silicon) method on a major surface of the P-type silicon substrate and, for example, a device region
3
of a T shape is defined by the element isolation insulating film
2
. Further, directions of sides of the device region
3
are parallel or perpendicular to the orientation flat and coincides with the <110> crystallographic orientation of the major surface of the silicon substrate
1
. The device regions
3
, that is active regions, are of a T shape each and arranged systematically across the major surface of the P-type silicon substrate.
A plurality of gate electrodes
5
each functioning as a word line of a memory cell are formed in parallel to one another on the surface of the substrate
1
with a thin gate oxide film
4
interposed therebetween. Further, an N-type diffusion layer
7
is formed in the device region
3
on the substrate surface by ion implantation of an N-type impurity with the gate electrode
5
and resist
11
thereon as a mask for gate patterning.
Then, description will be given of a fabrication process of the DRAM, especially of the step of forming an element isolation insulating film by means of the LOCOS method.
FIGS. 4A
to
4
H are sectional views, in sequential steps, showing a method for forming a LOCOS oxide film in a conventional DRAM fabrication process. As shown in
FIG. 4B
, a thermal oxide film
12
is formed to, for example, a thickness of 10 nm on a surface of a silicon substrate
1
shown in
FIG. 4A and
, as shown in
FIG. 4C
, a silicon nitride film
13
is deposited on the thermal oxide film
12
with, for example, thickness of 120 nm.
Thereafter, as shown in
FIG. 4D
, the silicon nitride film
13
is patterned so as to produce a field pattern by means of a lithography technique.
Then, as shown in
FIG. 4E
, the surface of the substrate is thermally oxidized, for example, at 980° C. to form a field oxide film
2
to a thickness of, for example, 400 nm.
Subsequent to the thermal oxidation, as shown in
FIG. 4F
, the silicon nitride film
13
is removed and the silicon oxide film
12
beneath the silicon nitride film
13
is further removed.
Thereafter, as shown in
FIG. 4G
, boron ions
6
are implanted all over the wafer surface to form a channel stopper layer
14
under conditions of a dose at 1×10
12
/cm
2
and an acceleration energy at 1000 keV.
After the ion implantation, as shown in
FIG. 4H
, ion implantation of an N-type impurity
16
is effected to form a diffusion layer
7
of the N-type impurity in the device region with the field oxide film
2
as a mask.
A series of the steps including formation of a field oxide film by means of the LOCOS method, formation of a gate electrode (a word line) and formation of a diffusion layer are repeated and a DRAM is eventually completed.
Generally, a semiconductor device has been miniaturized and highly integrated so as to increase a fabrication yield of chips obtained from a wafer. In a case of DRAM, a 16 Mbit DRAM has been fabricated under design rules of the minimum line width, the minimum element isolation width for insulation (a width of a field oxide film formed by means of the LOCOS method for isolating devices from one another) and a gate length, all at 0.5 &mgr;m. However, when a 64 Mbit DRAM is fabricated under the same dimension as those of a 16 Mbit DRAM, an area per chip becomes four times so that the number of chips obtained from a wafer decreases to one-fourth. For this reason, a 64 Mbit DRAM adopts design rules of the minimum line width, the minimum element isolation width for insulation and a gate length, all at 0.35 &mgr;m, so as to restrict a chip area to 1.5 times the chip area of a 16 Mbit DRAM and in turn prevent a chip yield from decreasing by a great margin.
In such a way, when dimensions in a plan is smaller, there arises a necessity to decrease a dimension in a height direction as well. Therefore, a thickness of the field oxide film was 400 nm for a 16 Mbit DRAM, but the thickness is decreased to 300 nm for a 64 Mbit DRAM, and a thickness of a gate oxide film is also decreased from 15 nm to 11 nm.
However, in such higher integration of a semiconductor device, an element isolation withstand voltage and a gate withstand voltage are deteriorated, which were not problematic for a conventional 16 Mbit DRAM, with the result that a problem has arisen because of increase in the number of defective chips.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a fabrication process therefor in which an element isolation withstand voltage can be prevented from lowering and a fabrication yield of a miniaturized, highly integrated semiconductor device can be improved.
A semiconductor device according to the present invention is constituted such that a surface of a substrate is subjected to an oxidation treatment at a temperature equal to or higher than 1050° C. to form an oxide film with a thickness equal to or more than 1500 nm and thereafter, the oxide film is removed, thereby decreasing a density of pits existing at the surface of a substrate to a value thereof equal to or less than a density of pits prior to the oxidation treatment.
Another semiconductor device according to the present invention is constituted such that a surface of a substrate is subjected to an oxidation treatment at an oxidation speed equal to or higher than 7.5 nm/min to form an oxide film of a thickness equal to or more than 1500 nm and thereafter, the oxide film is removed, thereby decreasing a density of pits existing at the surface of a substrate to a value thereof equal to or less than a density of pits prior to the oxidation treatment.
Still another semiconductor device according to the present invention is constituted such that a surface of a substrate is subjected to an oxidation treatment at a temperature equal to or higher than 1050° C. to form an oxide film of a thickness equal to or more than 1500 nm and thereafter, the oxide film is removed, thereby decreasing a depth of a pit existing at the surface of a substrate to a value equal to or less than 50 nm.
Yet another semiconductor device according to the present invention is constituted such that a surface of a substrate is subjected to an oxidation treatment to form an oxide film and thereafter, the oxide film is removed, thereby decreasing a depth of a pit existing at the surface of a substrate to a value equal to or less than 50 nm.
Further, a gettering film such as a polysilicon film can be formed on a back surface of the semiconductor substrate.
A fabrication process for a semiconductor device according to the present invention comprises the steps of oxidizing surfaces of a substrate at a temperature equal to or higher than 1050° C. to form oxide films each of a thickness equal to or more than 1500 nm; and thereafter, effecting element isolation of the sur

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