Fabrication of two-level polysilicon devices

Details Fabrication of two-level polysilicon devices Fabrication of two-level polysilicon devices

1978-12-29

1980-12-23

Tupman, W. C.

Metal working

Method of mechanical manufacture

Assembling or joining

29580, 29591, 156653, 156657, 156662, 357 59, B01J 1700

Patent

active

042401968

ABSTRACT:
In a two-level overlapping polysilicon device even the slightest amount of undercutting of an oxide layer (12) which underlies a first polysilicon layer (14) can lead to unacceptably low breakdown voltages in the device. In accordance with the invention, the first polysilicon and oxide layers of an LSI MOS wafer are defined as usual. But then the standard fabrication process is modified to etch the first polysilicon layer back beyond the edge of the oxide undercut. Subsequently, the structure is reoxidized and a second polysilicon layer (22) deposited and patterned. The modified process is characterized by the absence of any oxide thinning between the first and second polysilicon layers or between the second polysilicon layer and the substrate (10) of the device. As a result, voltage breakdown problems in the individual chips of the wafer are thereby greatly reduced and the yield of the wafer significantly increased.

REFERENCES:
patent: 3551196 (1970-12-01), Herczog
patent: 3906620 (1975-09-01), Anzai

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