Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-05-24
2001-02-06
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
Reexamination Certificate
active
06184069
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for manufacturing thin film transistor-liquid crystal displays and, more specifically, to a process for manufacturing thin film transistor-liquid crystal displays with self-aligned transparent conducting layers.
BACKGROUND OF THE INVENTION
Liquid crystal displays (LCD) are widely applied in electrical products, such as digital watches, calculators, etc. Moreover, with the advance of techniques for manufacture and design, the thin film transistor-liquid crystal display (TFT-LCD) is being introduced into portable computers, personal digital assistants, color televisions, and is replacing gradually the CRTS that are used for conventional displays. However, following the design rules of TFT-LCD to large scale devices, there are many problems and challenges, such as low yields and low throughput, in developing large scale TFT-LCDs devices.
In general, the TFT-LCD comprises a bottom plate on which is formed thin film transistors and pixel electrodes, and a top plate on which is constructed color filters. The liquid crystal molecules are filled between the top plate and the bottom plate. In their operation, a signal voltage is applied to the TFT that is the switching element of each unit pixel. The TFT receives the signal voltage, then turns on so that data voltage carrying image information can be applied to the corresponding pixel electrode and the liquid crystal via the TFT. The arrangement of the liquid crystal molecules is changed, thereby the optical properties are changed and the image is displayed.
The typical structure of the conventional TFT-LCD is illustrated in
FIG. 1
, wherein a gate
4
and a storage capacitor electrode
6
are formed on a substrate
2
. An insulating layer
8
is formed on the substrate
2
to cover the gate
4
and the storage capacitor electrode
6
. An a-silicon layer
10
is formed above the insulating layer
8
and the gate
4
, and an n+ a-silicon layer
12
is deposited on the top surface of the a-silicon layer
10
. In additional, source/drain (S/D) structures
14
are formed above the n+ a-silicon layer
12
. It is noted that data lines
16
are also formed on the insulating layer
8
at the same time while the S/D structures
14
are defined. Moreover, a passivation layer
18
is formed on the substrate
2
to cover the S/D structures
14
, the a-silicon layer
10
and the data lines
16
. A contact hole
20
is formed on the passivation layer
18
to expose the surfaces of the S/D structures
14
. An indium tin oxide (ITO) layer
22
is formed on the passivation layer
16
to connect the S/D structures
14
electrically.
It is noted that the ITO layer deposited on the passivation layer
18
is enlarged as much as possible, even overlaping the scan lines and data lines, for promoting the open ratio, as shown in
FIG. 1
, in order to increase the brightness of the TFT-LCD. However, the parasitic capacitor effect always occurs in the TFT-LCD structures due to the said overlapping, and causes interference between signals applied on the ITO electrodes and signals transferred from the adjacent data lines. A proposal to solve the issue is to form the TFT-LCD structure as illustrated in
FIG. 2
, wherein a portion of the ITO layer
22
is removed for preventing the residual ITO layer
22
from covering the data lines
16
. However, the open ratio is reduced after removing the portion of the ITO layer
22
. Thus, how to enlarge the area of the ITO electrode as much as possible and make the ITO electrode not overlap the scan lines and the data lines are current important issues.
SUMMARY OF THE INVENTION
The prime objective of the present invention is to provide a method for manufacturing a TFT-LCD display with self-aligned transparent conducting layers.
The second objective of the present invention is to provide a structure of TFT-LCD devices, wherein the edges of the transparent conducting layer are aligned to an edges of the data lines and the scan lines below.
The another objective of the present invention is to promote the open ratio of the transparent conducting layer in manufacturing the TFT-LCD devices.
The further objective of the present invention is to provide a method for manufacturing a TFT-LCD device using two exposure steps for reducing exposure defects.
A method for forming a TFT-LCD with a self-aligned transparent conducting layer over a substrate comprises the following steps. Initially, a first metal layer is formed on the substrate to define a gate structure, a scan line and a storage capacitor electrode on the substrate. Then, an insulating layer is formed on the first metal layer and the substrate. A silicon layer is formed above the insulator layer and the gate structure. A doped silicon layer is formed above the silicon layer, then a second metal layer is formed on said substrate to define S/D structures and data lines. Then, a passivation layer is formed on the second metal layer, a-silicon layer, and insulating layer, wherein the passivation layer has a contact hole for exposing the top surface of the S/D structure. A transparent conducting layer is formed on the passivation layer and the S/D structures.
Then, a negative photoresist is formed on the transparent conducting layer. A front-side exposure step is performed to pattern the negative photoresist by using a first photomask with openings corresponding to the contact hole and the storage capacitor electrode. Additionally, a back-side exposure step is performed by using the first metal layer and the second metal layer as the second photomask. After removing the unexposed negative photoresist, an etching step is performed to define a transparent conducting layer by using the residual negative photoresist. Thus, the edge of transparent conducting layer is aligned to the edge of data lines.
REFERENCES:
patent: 5010027 (1991-04-01), Possin et al.
patent: 5130263 (1992-07-01), Possin et al.
patent: 5637519 (1997-06-01), Tsai et al.
Bowers Charles
Chi Mei Electronics Corp.
Christianson Keith
LandOfFree
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