Fabrication of stacked dielectric layer for suppressing...

Details Fabrication of stacked dielectric layer for suppressing... Fabrication of stacked dielectric layer for suppressing...

2007-04-17

2007-04-17

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S618000, C438S622000, C438S435000

Reexamination Certificate

active

10842971

ABSTRACT:
A method of fabricating a stacked dielectric layer for suppressing electrostatic charge buildup. First, a substrate having metal layers thereon is provided, with a plurality of gaps formed therebetween. Next, a dielectric layer is formed by simultaneous deposition and ion-bombardment, such that the dielectric layer covers the bottom dielectric liner and fills the gaps. Finally, a top dielectric liner is formed on the dielectric layer by deposition without ion-bombardment. Furthermore, the present invention provides another method to fabricate a stacked dielectric layer by performing a plasma treatment on the dielectric layer to suppress electrostatic charge buildup. As a result, the above-mentioned methods can efficiently avoid metal extrusion issues.

REFERENCES:
patent: 5605859 (1997-02-01), Lee
patent: 5741740 (1998-04-01), Jang et al.
patent: 5786278 (1998-07-01), Fry
patent: 6159842 (2000-12-01), Chang et al.
patent: 6265321 (2001-07-01), Chooi et al.
patent: 6531377 (2003-03-01), Knorr et al.
patent: 2003/0132430 (2003-07-01), Tsai

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