Fabrication of semiconductor devices

Details Fabrication of semiconductor devices Fabrication of semiconductor devices

2001-09-27

2003-07-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S640000, C438S043000

Reexamination Certificate

active

06586327

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to microelectronic devices and there fabrication.
BACKGROUND OF THE INVENTION
A substantial portion of the cost of microelectronic device fabrication is attributable to the capital cost of lithography equipment. Such equipment produces integrated circuits by drawing patterns on a substrate using commonly known methods, such as photolithography, e-beam lithography, as well as many others. Photolithography requires the use of expensive patterned masks. Exposure of the substrate to UV radiation through the mask pattern, followed by etching, forms circuit traces on the substrate. A microscopic electronic device is formed through repetition of this elaborate process so as to generate a series of adjacent stacked circuit layers. The cost of fabrication increases as the device geometry becomes more complex and the feature size diminishes. For features smaller than 1 &mgr;m, e-beam lithography may be needed to create the masks, and deep UV (X-ray) exposure systems may be necessary to perform the substrate lithography. With e-beam lithography, an electron beam is used to draw the features on the surface of the substrate of the masks. This process is very slow because the features are typically drawn sequentially by a single electron beam. Furthermore, multiple lithography steps must be aligned to one another for the resulting device to be operational.
Another method of microelectronic device fabrication is the “dual-damascene” process. Basically, this technique involves etching a trench in a substrate, etching a deeper channel (i.e., a via) within the trench, electrochemically plating an active layer within the trench and the via, and removing the overfill by chemical mechanical polishing (CMP). Currently, only a single material layer (i.e., copper and, possibly, a barrier and/or sticking layer) is plated within the etched trench and via. As a result, this process is limited in terms of the circuitry it can be used to create. Furthermore, the trenches and vias are patterned photolithographically.
Accordingly, there exists a need for a microelectronic device fabrication process that does not use masks or lithography and is not limited to a single material layer.
SUMMARY OF THE INVENTION
The present invention is directed to a microelectronic device fabrication process which, in some embodiments, does not require the use of masks or lithography. This is accomplished through creation of a recessed pattern on a substrate. A series of layers is applied to the substrate surface and the recessed surfaces, and the substrate surface may then be planarized (e.g., by polishing) to a desired degree. Planarization removes one or more of the deposited layers, or a portion of a layer, from the substrate surface but not from within the recessed pattern. Consequently, the depth of a recessed feature determines the number of layers that will remain therein at the conclusion of processing.
In one aspect, therefore, the invention is directed to fabricating a microelectronic device on a substrate having a recessed contour pattern. After the pattern is defined (e.g., by molding, as discussed below, or by etching or other conventional processes) a series of layers each having a predetermined electrical property is applied. The device is planarized (e.g., by polishing) to remove one or more layers thus far applied. Planarization does not affect deposited material within the recessed pattern. The devices is further processed, typically by etching, to further remove material from one or more layers thus far applied and exposed through planarization. Ultimately, the stacked layers are disposed within the contour pattern, and some of the layers also reside on the substrate. The layers cooperate to form the microelectronic device.
In another aspect, the invention relates to fabrication of an electronic devices using a molded substrate. This approach avoids the need to etch a microscopic pattern into the substrate. In accordance with this aspect of the invention, a form having a raised topology complementary to a desired microscopic pattern of features is created. The form is applied to a moldable substrate to impose the pattern therein, i.e., to create a recessed pattern complementary to the raised topology. A series of layers having desired electrical properties is applied to the recessed pattern, thereby creating the electronic device. In one embodiment, the form is fabricated by etching a pattern into a master substrate, plating the patterned master substrate, and electroforming on a metal plate a topology complementary to the etched pattern to serve as a form. The form may be used to impose the original pattern onto a moldable substrate by, e.g., injection molding. The pattern may, for example, comprise pyramidal, square and/or round pits and square, rounded and/or V-groove channels.
In one exemplary embodiment, the invention is used to fabricate a memory device in accordance with any of U.S. Pat. Nos. 3,245,051, 5,673,218 and 5,889,694. In this case, the recessed pattern includes a first series of channels running in a first direction and a second series of channels running in a second direction substantially perpendicular to the first direction. These are imposed (e.g., by molding, as discussed above) into a non-conducting substrate. The first-series channels and the second-series channels cross at crossing points, and pits are located at the crossing points. The applied layers form nonlinear elements (e.g., diodes) in some of the pits, depending on their depths. Each nonlinear element connects a first-series channel with a second-series channel. The nonlinear elements are distributed among the pits in a scheme that defines the data contents of the memory. A connection between crossing channels signifies one binary bit state (e.g., zero) and no connection signifies the other binary bit state (e.g., one).


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Copy of International Search Report for PCT/US01/30296 (4 pgs.).
“Aries Process Notes: Oxide Planarization”, Materials Research Corporation, 2 pages.
Chip Scale Review Online, http://www.chipscalereview.com/issues/0301/techReport.html, printed on Sep. 17, 2001, 3 pages.
Damascene, http://courses.nus.edu.sg/course/phyweets/Projects99/Copper/damascene.htm, printed on Sep. 26, 2001, 8 pages.
Dual-Damascene: Overcoming Process Issues—SI Jun. 2000, http://www.semiconductor.net/semiconductor/issues/2000/200006/six0006dual.asp, printed on Sep. 17, 2001, 7 pages.
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