Fabrication of self-aligned front gate and back gate of a...

Details Fabrication of self-aligned front gate and back gate of a... Fabrication of self-aligned front gate and back gate of a...

2000-10-16

2002-05-07

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C257S347000, C257S366000

Reexamination Certificate

active

06383904

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor in SOI (semiconductor on insulator) technology with a front gate and a back gate that are self-aligned for minimizing short-channel effects in the field effect transistor.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate structure
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate structure
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate structure
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are scaled down further, the junction capacitances formed by the drain and source extension junctions
104
and
106
and by the drain and source contact junctions
108
and
112
may limit the speed performance of the MOSFET
100
. Thus, referring to
FIG. 2
, a MOSFET
150
is formed with SOI (semiconductor on insulator) technology. In that case, a layer of dielectric material
152
is formed on the semiconductor substrate
102
, and a layer of semiconductor material
154
is formed on the layer of dielectric material
152
. A drain
156
and a source
158
of the MOSFET
150
are formed in the layer of semiconductor material
154
. Elements such as the gate dielectric
116
and the gate structure
118
having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function. Processes for formation of such elements
116
,
118
,
152
,
154
,
156
, and
158
of the MOSFET
150
are known to one of ordinary skill in the art of integrated circuit fabrication.
In
FIG. 2
, the drain
156
and the source
158
are formed to extend down to contact the layer of dielectric material
152
. Thus, because the drain
156
, the source
158
, and a channel region
160
of the MOSFET
150
do not form a junction with the semiconductor substrate
102
, junction capacitance is minimized for the MOSFET
150
to enhance the speed performance of the MOSFET
150
formed with SOI (semiconductor on insulator) technology.
In addition, referring to
FIGS. 1 and 2
, as the dimensions of the MOSFETs
100
and
150
are scaled down further, the occurrence of undesired short-channel effects increases, as known to one of ordinary skill in the art of integrated circuit fabrication. With short-channel effects, the threshold voltage of the MOSFET changes such that electrical characteristics of such a MOSFET become uncontrollable. For the MOSFET
150
formed with SOI (semiconductor on insulator) technology, a back gate region
162
is formed in the semiconductor substrate
102
below the layer of dielectric material
152
to minimize such undesired short-channel effects in the MOSFET
150
. The back gate region
162
is doped for enhanced conductivity of the back gate region
162
and for affecting the voltage potential through the channel region
160
, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, a voltage bias may be applied on the back gate region
162
for further controlling the electrical characteristics of the MOSFET
150
to compensate for the short-channel effects in the MOSFET
150
.
In the prior art MOSFET
150
, the back gate region
162
is first formed within the semiconductor substrate
102
before formation of any of the other elements
116
,
118
,
152
,
154
,
156
,
158
, and
160
of the MOSFET
150
. The back gate region
162
is first formed by implantation of a dopant into the back gate region
162
within the semiconductor substrate
102
. Then, the layer of dielectric material
152
and the layer of semiconductor material
154
are deposited on the layer of semiconductor material
154
. The gate dielectric
116
and the gate structure
118
are then formed on the semiconductor substrate
102
. Then, the drain
156
and the source
158
are formed with implantation of a dopant into the layer of semiconductor material
154
. Such process steps are known to one of ordinary skill in the art of integrated circuit fabrication.
In this process of the prior art, because the channel region
160
between the drain
156
and the source
158
is formed after formation of the back gate region
162
, to ensure that the back gate region
162
is aligned to be under the channel region
160
of the MOSFET
150
, the area of the back gate region
162
is formed to be larger than the area of the channel region
160
. The larger area of the back gate region
162
accounts for variations in alignment of the channel region
160
to the back gate region
162
when the area of the channel region
160
is defined after formation of the back gate region
162
.
However, a larger area of the back gate region
162
results in larger capacitance at the back gate region
162
of the MOSFET
150
which may limit the speed performance of the MOSFET
150
. The back gate region
162
forms a junction with the substrate
102
with junction capacitance at such a junction. In addition, the back gate junction
162
overlaps to be disposed under the drain
156
and the source
158
to form overlap capacitance between the back gate region
162
and the drain
156
and the source
158
. Such capacitances degrade the speed performance of the MOSFET
150
, and such capacitances increase with a larger area of the back gate region
102
.
Nevertheless, fabrication of the MOSFET in SOI (semiconductor on insulator) technology is desired because the junction capacitance at the drain and source of the MOSFET is minimized. Thus, a mechanism is desired for minimizing the area

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