Fabrication of MIM capacitor in copper damascene process

Details Fabrication of MIM capacitor in copper damascene process Fabrication of MIM capacitor in copper damascene process

2001-04-16

2002-05-14

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S250000, C438S393000

Reexamination Certificate

active

06387775

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of fabricating microelectronic devices and specifically to methods of fabricating metal-insulator-metal (MIM) capacitors.
BACKGROUND OF THE INVENTION
Fabrication of metal/insulator/metal (MIM) capacitors in copper (Cu) damascene is very challenging because a trench must be formed on the capacitor and the control of the capacitor thickness is difficult.
U.S. Pat. No. 5,946,567 to Weng et al and U.S. Pat. No. 6,001,702 to Cook et al. each describe processes for the fabrication of MIM capacitors.
U.S. Pat. No. 6,072,210 to Choi describes a capacitor process using a copper electrode.
U.S. Pat. No. 5,918,135 to Lee et al. describes a MIM capacitor fabrication process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an MIM capacitor while preserving the dielectric capacitor during the trench etch.
Another object of the present invention is to provide a method of fabricating an MIM capacitor with precise control of capacitor thickness with the associated capacitance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an exposed lower metal damascene is provided. A capacitor layer is formed over the semiconductor structure and the exposed lower metal damascene. An organic etch stop layer is formed upon the capacitor layer. An IMD layer is formed upon the organic etch stop layer. The IMD layer is etched with a first etch highly selective to the IMD layer as compared to the organic etch stop layer, to form an IMD trench exposing a portion of the organic etch stop layer. The exposed portion of the organic etch stop layer is etched with a second etch method highly selective to the exposed portion of the organic etch stop layer as compared to the capacitor layer, to expose a portion of the capacitor layer. An upper metal damascene is formed upon the exposed portion of the capacitor layer and within the IMD trench to complete formation of the MIM capacitor.


REFERENCES:
patent: 5918135 (1999-06-01), Lee et al.
patent: 5946567 (1999-08-01), Weng et al.
patent: 6001702 (1999-12-01), Cook et al.
patent: 6072210 (2000-06-01), Choi
patent: 6261951 (2001-07-01), Buchwalter et al.
patent: 6278147 (2001-08-01), Dalton et al.
patent: 6284149 (2001-09-01), Li et al.
patent: 6284619 (2001-09-01), Seymour et al.

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