Fabrication of integrated circuits with isolation trenches

Details Fabrication of integrated circuits with isolation trenches Fabrication of integrated circuits with isolation trenches

2008-08-21

2010-10-05

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S197000, C438S680000, C257SE21170, C257SE21249, C257SE21278, C257SE21293, C257SE21304, C257SE21315, C257SE21421

Reexamination Certificate

active

07807577

ABSTRACT:
After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

REFERENCES:
patent: 6265285 (2001-07-01), Tseng
patent: 6355524 (2002-03-01), Tuan et al.
patent: 7038291 (2006-05-01), Goda et al.
patent: 7303964 (2007-12-01), Shiraiwa et al.
patent: 7402886 (2008-07-01), Yuan
patent: 2008/0153234 (2008-06-01), Lee

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