Fabrication of integrated circuits with borderless vias

Details Fabrication of integrated circuits with borderless vias Fabrication of integrated circuits with borderless vias

2002-06-12

2003-05-06

Ngô, Ngân V. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S758000, C257S759000, C257S760000, C438S623000, C438S624000, C438S631000, C438S633000

Reexamination Certificate

active

06559045

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of borderless vias in intermetal dielectrics.
2. Description of the Related Art
As feature sizes in the production of integrated circuits approach 0.25 &mgr;m and below, problems of packing density become increasingly difficult to overcome. The formation of borderless vias is one method to reduce metal pitch in and packing density of integrated circuits. However, it is exceedingly difficult to form borderless vias in conventional subtractive interconnect patterning. The major problem is that deep and narrow trenches are produced at the side of metal lines in via etching whenever vias are misaligned to the underlying metal lines. The trench depth is extremely difficult to control since it is common practice to excess plasma etch in via etch to ensure that via holes are completely open. Organic byproducts are produced in dielectric plasma etching when opening via holes. Those byproducts accumulated at the bottom of trenches cannot be effectively removed by oxygen-based plasma or ashing which are commonly used techniques to strip photoresist used in integrated circuit fabrication. Liquid organic chemicals, which are also commonly used to remove organic byproducts, often cause corrosion of metals from which interconnects are made. As a result, via resistance can be very high and, thus, the performance and reliability of integrated circuits degrade. In extreme cases, integrated circuits fail to function when via holes are totally blocked and vias become electrically open.
The cause of the above mentioned issues of conventional architectures is the lack of a etchstop or plasma etch selectivity when opening vias. These occur in two different ways. First, the same kind of inorganic dielectric is typically used for the via-level and metal-level inter-level dielectrics (IMD□). Even when two different kinds of inorganic dielectrics are used, as far as plasma etching for via holes is concerned, the difference between these two kinds of inorganic dielectrics is insignificant. As a result, via etch continues even when via holes are already fully opened as long as there is misalignment between via and the underlying interconnects or metal lines. The use of two different kinds of dielectrics, one inorganic and the other organic, have been used for the metal-level and the via-level IMD□, respectively, in some prior architectures. This architecture does not have the aforesaid disadvantage architectures since there is very high plasma etch selectivity between inorganic and organic dielectrics. However, its weakness is associated with the photoresist, which is commonly used for patterning, a key technique in integrated circuit fabrication. In conventional integration methods, both the photoresist and the organic IMD□ are exposed at the completion of via etch. The organic via-level dielectric is attacked, resulting in deep trenches along the side of metal lines when removing the photoresist which is also organic.
According to the invention one ensures that the part of the via-level IMD, which is exposed to via etch plasma due to misalignment between via and metal lines, does not etch or only insignificantly etches in via openings and during resist removal following via etch. The invention provides borderless vias in integrated circuits. Two key elements are the use of dielectrics of significantly dissimilar plasma etch characteristics and that the dielectric immediately over metal lines is different from the dielectric at the sidewall of the metal lines. These objectives are achieved by dividing the metal-level IMD into two parts. One dielectric on the sidewall of the metal lines and the rest of the metal-level IMD between the dielectric on the side walls. The two dielectrics are significantly different from each other in their plasma etch characteristics. Another embodiment adds a hardmask layer between a photoresist layer and the organic dielectric for the via-level IMD so that either resist or the organic dielectric can be selectively removed. A hardmask is also necessary when the via-level IMD is inorganic and the etchstop, at the sidewall of metal lines, in via etch is organic. The hardmask can be either permanent or sacrificial. Performance enhancement of integrated circuits is achieved with the implementation of new architectures according to this invention in conjunction with the use of dielectrics of low dielectric constant.
SUMMARY OF THE INVENTION
The invention provides an integrated circuit structure which comprises
(a) a substrate;
(b) a layer of a second dielectric material positioned on the substrate;
(c) a plurality of spaced apart metal contacts on the layer of the second dielectric material, which metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls being filled with the second dielectric material; a top surface of each of the metal contacts, the linings and the spaces being at a common level;
(d) an additional layer of the second dielectric material on at least some of the metal contacts, linings and filled spaces; at least one via extending through the additional layer of the second dielectric material and extending to the top surface of at least one metal contact and optionally at least one of the linings.
The invention also provides an integrated circuit structure which comprises
(a) a substrate;
(b) a layer of a third dielectric material positioned on the substrate;
(c) a plurality of spaced apart metal contacts on the layer of the third dielectric material, which metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls being filled with a second dielectric material; a top surface of each of the metal contacts, the linings and the spaces being at a common level;
(d) an additional layer of the second dielectric material on at least some of the metal contacts, linings and filled spaces; an additional a layer of the third dielectric material positioned on the additional layer of the second dielectric material; at least one via extending through the additional layer of the third dielectric material and the additional layer of the second dielectric material and extending to the top surface of at least one metal contact and optionally at least one of the linings.
The invention further provides a process for producing an integrated circuit structure which comprises
(a) providing a substrate;
(b) depositing a layer of a second dielectric material on the substrate;
(c) forming a pattern of metal contacts on the layer of the second dielectric material;
(d) conformally depositing a lining of a first dielectric material on side walls of the metal contacts, on a top surface of the metal contacts, and on a floor of a space between the metal contacts on the layer of the second dielectric material;
(e) removing the first dielectric material from the top surface of the metal contacts while retaining the first dielectric material lining on the side walls of the metal contacts;
(f) depositing an additional layer of the second dielectric material on the top surface of the metal contacts and in the space between adjacent linings of the metal contacts;
(g) depositing a layer of a sacrificial metal on the additional layer of the second dielectric material;
(h) depositing a layer of a photoresist on the layer of the sacrificial metal layer;
(i) imagewise removing a portion of the photoresist over at least one metal contact and optionally over at least a portion of the lining of first dielectric material on a side wall of a metal contact;
(j) removing the portion of the layer of the sacrificial metal under the removed portion of the photoresist;
(k) removing the balance of the photoresist layer, and removing the portion of the additional layer of the second

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