Fabrication of improved low-k dielectric structures

Details Fabrication of improved low-k dielectric structures Fabrication of improved low-k dielectric structures

2000-04-25

2002-09-03

Markoff, Alexander (Department: 1746)

Etching a substrate: processes

Gas phase etching of substrate

Irradiating, ion implanting, alloying, diffusing, or...

C216S017000, C216S067000, C216S018000, C438S725000, C438S637000

Reexamination Certificate

active

06444136

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of fabrication of structures in semiconductor chips. In particular, the invention is in the field of fabrication of structures using low dielectric constant (“low-k”) material.
2. Background Art
It is known in the art that a dielectric material used in the fabrication of integrated circuit structures should have a low dielectric constant (“low-k”). The advantages of using low dielectric constant material in such structures are well-known. One of the advantages is a reduction in the inter-line coupling capacitance between metal lines. Such capacitance causes “noise” or “crosstalk” between metal lines. Another advantage is the reduction of capacitance between different layers of interconnect and also a reduction of capacitance between a layer of interconnect to the substrate. It is known in the art that a lower capacitance will reduce the interconnect metal line delay, i.e. the “RC” delay. Another advantage is the significant decrease in power consumption resulting from the lower capacitance since the amount of power consumed is directly proportional to the capacitance. Thus, it is generally appreciated in the art that the use of low dielectric constant material in the fabrication of integrated circuit structures is desirable for the reasons mentioned above.
Silicon dioxide is one of the dielectric materials used in the fabrication of integrated circuit structures because of its desirable features such as adequate hardness, and ease of cleaning and etching for even small feature sizes. However, the dielectric constant value of silicon dioxide is about 4.0. It is generally appreciated in the art that this dielectric constant value is too high. Thus, there is a drive to utilize materials with lower dielectric constant values in the fabrication of integrated circuit structures.
Polymers with a dielectric constant value of 2.5 or 3.0 are achievable. One method of reducing the dielectric constant of some polymer films is to increase the porosity of the polymer by introducing air into the pores of the polymer. Since the dielectric constant value of air is 1.0, introducing air into the material decreases the dielectric constant value of the material.
However, there are also problems associated with the use of lower dielectric constant material in the fabrication of integrated circuit structures. For example, etching low-k dielectric is difficult. Most low-k dielectrics are easily damaged by the etch chemistry or plasma. As an example, hydrogen silsesquioxane (also referred to as “HSQ”) is a low-k dielectric which has been used in the fabrication of integrated circuits. However, the silicon-hydrogen bond in hydrogen silsesquioxane is weak and can easily be broken. Once the silicon-hydrogen bond is broken, the remaining material exhibits a tendency to absorb moisture. Also, during etching of most low-k dielectrics, polymers are generated which are hard to clean without etching away the low-k dielectric itself.
In addition, most low-k dielectrics have poor mechanical strength. One reason poor mechanical strength is undesirable is because low-k dielectric may not withstand chemical mechanical polishing (“CMP”). It is known in the art that the CMP process is usually used to remove excess metal over the wafer surface after the metal has been used to create damascene structures.
Thus, problems associated with the use of a low-k dielectric material in the fabrication of integrated circuit structures include (a) difficulty in etching and cleaning low-k dielectric materials; (b) undesirable absorption of moisture; and (c) low mechanical strength of low-k dielectric materials.
It is known that when dielectric material is exposed to electron beams (E-beams) or ion beams (I-beams), the properties of the dielectric material can be changed. For example, a paper entitled “E-Beam Curing Process of Low-K Dielectrics for unlanded vias in 0.25 &mgr;m CMOS Technology” by David Feiler, Q. Z. Liu, and Maureen R. Brongo discusses an E-beam curing process of low-k dielectrics for unlanded vias in a CMOS technology. It is shown in that paper that the properties of the low-k dielectric can be modified so as to prevent unlanded vias from penetrating too deeply into the underlying low-k dielectric.
A second paper entitled “A Novel and Low Thermal Budget Planarization Scheme for Pre- and Inter-Metal Dielectric Using HSQ (Hydrogen Silsesquioxane) Based SOG with Electron-Beam Curing for 256 Mbit DRAM and Beyond” by Juseon Goo, Hae-Jeong Lee, Seong Ho Kim, Ji Hyun Choi, Byung Keun Hwang, Ho-Kyu Kang, and Moon Yong Lee discusses a finding that hydrogen silsesquioxane can be cured and densified with exposure to E-beams.
A third paper entitled “Integration of Low k Spin-on Polymer (SOP) Using Electron Beam Cure for Non-Etch-Back Application” by Jane C. M. Hui, Yi Xu, Chow Yeog Foong, Liao Marvin, Lin Charles, and Lin Yih Shung discusses an E-beam curing process for spin-on glass materials in relation to spin-on polymer non-etch-back processing such as “via poisoning.” It is shown that after E-beam exposure, the tested materials' properties had changed, e.g. lower moisture content, higher film density and higher resistance were achieved.
A fourth paper entitled “Effects of Electron Beam Exposure on Poly(arylene Ether) Dielectric Films” by J. S. Drage, J. J. Yang, D. K. Choi, R. Katsanes, K. S. Y. Lau, S.-Q. Wang, L. Forester, P. E. Schilling, and M. Ross discusses the effects of E-beam exposure on chemical and physical properties of an organic dielectric film. Specifically, solvent resistance, glass transition temperature, and dielectric constant of the film are studied. The results of the study indicate that E-beam curing does not raise the dielectric constant compared to thermally-cured film.
In addition to the above-discussed papers, there are patents utilizing methods that alter the physical properties of dielectric materials using ion implantation. One such patent is U.S. Pat. No. 5,496,776 entitled “Spin-On Glass Planarization Process With Ion Implantation.” This patent discloses a method for planarizing an integrated circuit surface with a spin-on-glass sandwich layer, where the entire surface area of spin-on-glass exposed within a via etched through the spin-on-glass sandwich layer is not susceptible to sorption and outgassing of moisture. The patent also teaches a method of planarizing an integrated circuit surface which does not result in metallurgy and high resistivity problems associated with metallic interconnections through vias etched through the planarizing layer. One step in these methods is the implantation of ions into and through a spin-on-glass layer under various conditions. This method eliminates the need for an etch back process for the spin-on-glass exposed within the etched vias prior to metal deposition into those etched vias.
U.S. Pat. No. 5,192,697 entitled “SOG Curing By Ion Implantation” discloses among other things, a method of curing the spin-on-glass layer of an article which results in similar or better dielectric strength than a temperature cure method. Ions, such as argon or arsenic are implanted into the spin-on-glass layer of an article. The action of the ions moving through the spin-on-glass layer causes heating. This heating cures the spin-on-glass layer of the article.
U.S. Pat. No. 5,413,953 entitled “Method Of Planarizing An Insulator On A Semiconductor Substrate Using Ion Implantation” discloses an improved process for fabricating planar field oxide structures on a silicon substrate. The patent also discloses an improved process for fabricating planar Field Oxide (FOX) isolation structures and an improved process for fabricating planar insulating layers over patterned conducting layers by ion implantation and etching.
As part of these processes, the substrate surface is implanted with arsenic or phosphorus ions. This ion implantation results in a damaged oxide layer, which etches approximately 2 to 4 times faster than the undamaged portion of the field oxide. As a result

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