Fabrication of high resistive loads utilizing a single level pol

Details Fabrication of high resistive loads utilizing a single level pol Fabrication of high resistive loads utilizing a single level pol

1988-08-11

1989-08-22

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156652, 156656, 156657, 1566591, 156662, 156653, 357 2311, 357 42, 357 44, 357 59, 437 34, 437 41, 437200, 437201, H01L 21306, B44C 122, C23F 102, C03C 1500

Patent

active

048592781

ABSTRACT:
This invention relates to a method of fabricating high resistive loads utilizing a single level polycide process in very large scale integrated circuits. By etching away a top silicide layer which exposes an underlying polysilicon layer and then implanting with a heavy dose of boron, a high resistive load on the integrated circuit is formed. Very often the highly resistive polysilicon load is implemented as a second polysilicon layer, which increases the process complexity vastly. This invention discloses the use of only one polycide layer to implement both the low resistive gate and interconnect and the high resistive polysilicon load needed to implement certain circuit functions.

REFERENCES:
patent: 4451328 (1984-05-01), Dubois
patent: 4453306 (1984-06-01), Lynch et al.
patent: 4640844 (1987-02-01), Neppl et al.
patent: 4740479 (1988-04-01), Neppl et al.
patent: 4782033 (1988-11-01), Gierisch et al.
patent: 4786611 (1988-11-01), Pfiester

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