Fabrication of gate of P-channel field effect transistor...

Details Fabrication of gate of P-channel field effect transistor... Fabrication of gate of P-channel field effect transistor...

2001-04-04

2002-04-23

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

C438S306000

Reexamination Certificate

active

06376323

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a P-channel field effect transistor having a doped gate electrode with an added implantation of boron before patterning of the gate electrode and with a nitrided gate dielectric to minimize boron diffusion into the gate dielectric such that a thick gate electrode with minimized depletion region may be formed even with shallow drain and source extensions.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of is monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET
100
. Short-channel effects that result due to the short length of the channel between the drain extension
104
and the source extension
106
of the MOSFET
100
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET
100
become difficult to control with bias on the gate electrode
118
with short-channel effects which may severely degrade the performance of the MOSFET.
As the dimensions of the MOSFET
100
are further scaled down to tens of nanometers, short channel effects are more likely to disadvantageously affect the operation of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to
FIG. 1
, to prevent short channel effects, the drain and source extension junctions
104
and
106
are formed to be as shallow as possible, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIG. 2
, in the prior art, the drain and source extension junctions
104
and
106
are formed by implantation of a P-type dopant when the MOSFET
100
is a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor). A relatively heavy P-type dopant such as boron fluoride (BF
2
) is implanted such that the drain and source extension junctions
104
and
106
are shallow to minimize short channel effects. The gate electrode
118
that is comprised of a semiconductor material such as polysilicon is also doped with the boron fluoride (BF
2
) during such an implantation process. However, because the parameters in the implantation process are designed for forming the drain and source extension junctions
104
and
106
that are shallow, the boron fluoride (BF
2
) dopant may not extend down into the gate electrode
118
toward the gate dielectric
116
. The gate electrode
118
is desired to have a relatively large height such that a thick silicide may be formed with the gate electrode
118
to minimize resistance at the gate of the MOSFET
100
. With minimized P-type dopant near the gate dielectric
116
, a depletion region
130
forms toward the bottom of the gate electrode
118
near gate dielectric
116
. Such a depletion region
130
is disadvantageous because such a depletion region increases the effective gate capacitance to degrade the speed performance of the MOSFET
100
. In addition, such a depletion region
130
disadvantageously increases the threshold voltage of the MOSFET
100
.
Furthermore, the gate dielectric
116
is comprised of silicon dioxide (SiO
2
) in the prior art, and such as gate dielectric
116
draws the P-type dopant away from the gate electrode
118
and into the gate dielectric
116
. Thus, the disadvantageous depletion region
130
is more likely to be formed when the gate dielectric is comprised of silicon dioxide (SiO
2
).
For increasing the concentration of the P-type dopant toward the bottom of the gate electrode
118
near gate dielectric
116
, the implantation energy and the concentration of the boron fluoride (BF
2
) dopant may be increased during the implantation process of FIG.
2
. However, such an increase of the implantation energy increases the depth of the drain and source extension junctions
104
and
106
to disadvantageously increase short channel effects of the MOSFET
100
. In addition, an increase of concentration of boron fluoride (BF
2
) with the increase of fluorine concentration may corrode the gate dielectric
116
.
Thus, a mechanism is desired for increasing the concentration of a P-type dopant near the gate dielectric of the PMOSFET to avoid formation of the depletion region near the gate dielectric while maintaining the drain and source extension junctions to be shallow for minimizing short channel effects.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, an added implantation process is performed to implant a P-type dopant into a layer of gate electrode material before the gate electrode is patterned from the layer of gate electrode material and before the drain and source extension junctions are formed. In addition, a nitrided gate dielectric material is used to prevent diffusion of the P-type dopant out of the gate electrode material and into the gate dielectric material.
In one embodiment of the present invention, for fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and the gate dielectric material contains nitrogen. A layer of gate electrode material is deposited on the layer of gate dielectric material. A first P-type dopant is implanted into a first region of the layer of

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