Fabrication of gate and diffusion contacts in self-aligned conta

Details Fabrication of gate and diffusion contacts in self-aligned conta Fabrication of gate and diffusion contacts in self-aligned conta

1998-05-29

2000-12-12

Saasat, Mahshid

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438233, 438634, 438702, H01L 214763

Patent

active

061598445

ABSTRACT:
Disclosed is a method for fabricating conductive contacts in a dielectric layer that overlies a semiconductor wafer having diffusion regions, shallow trench isolation regions, and gate structures that have a part overlying the shallow trench isolation regions. The method includes forming an oxide layer over the gate structures and forming a photoresist mask over the semiconductor wafer, including the oxide layer over the gate structures. The photoresist mask has windows that define an opening over gate contact locations, and the gate contact locations are defined substantially over the part of the gate structures that overlie the shallow trench isolation regions. The method further includes etching the oxide layer over the gate structures through the windows to define exposed gate structure regions. The method also includes depositing a silicon nitride layer over the semiconductor wafer including the oxide layer over the gate structures and the exposed gate structure regions, and depositing a dielectric layer over the deposited silicon nitride layer. The method then includes etching via holes through the dielectric layer and the silicon nitride layer to define conductive contact vias to both the exposed gate structure regions and diffusion regions.

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Unknown, "Advanced Interconnection and Contact Schemes Based on TiSi.sub.2 and CoSi.sub.2 : Relevant Materials Issues and Technological Implementation", Jun. 1988, pp. 144-153, Imec, Katholieke Universiteit Leuven.

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