Fabrication of FETs with source and drain contacts aligned with

Details Fabrication of FETs with source and drain contacts aligned with Fabrication of FETs with source and drain contacts aligned with

1984-06-12

1989-04-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437200, 437162, 437 41, 437984, H01L 21225

Patent

active

048227544

ABSTRACT:
A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.

REFERENCES:
patent: 4319395 (1982-03-01), Lund et al.
patent: 4343082 (1982-08-01), Lepselter et al.
patent: 4453306 (1984-06-01), Lynch et al.
Proposed for publication in IEEE Electron Device Letters: "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes," by D. S. Oh and C. Kim.

Affiliated with

Also associated with

Rating

Fabrication of FETs with source and drain contacts aligned with does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of FETs with source and drain contacts aligned with , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of FETs with source and drain contacts aligned with will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2396859