Fabrication of FETs

Details Fabrication of FETs Fabrication of FETs

1983-05-27

1984-06-12

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 156656, 357 67, H01L 21285

Patent

active

044533063

ABSTRACT:
A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.

REFERENCES:
patent: 3306788 (1967-02-01), Sterling et al.
patent: 4319395 (1982-03-01), Lund et al.
patent: 4343082 (1982-08-01), Lepselter et al.

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