Fabrication of deformable leads of microelectronic elements

Details Fabrication of deformable leads of microelectronic elements Fabrication of deformable leads of microelectronic elements

1999-10-27

2001-04-24

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S461000

Reexamination Certificate

active

06221750

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabrication of leads on microelectronic elements such as semiconductor wafers and chips and to microelectronic elements having such leads thereon.
BACKGROUND OF THE INVENTION
Microelectronic elements such as semiconductor chips typically are formed as solid elements with contacts on a front face. For example, semiconductor chips are typically formed by processing a large, flat disk-like wafer to form the internal electronic components of numerous semiconductor chips, the elements of each of such chip being disposed within a small, typically rectangular region of the wafer. The pads in each region are connected to the internal electronic components in that region. Typically, a passivation layer is applied on the front surface of the layer and provided with openings aligned with the pads. The passivation layer protects the internal components of the layer from contamination. After the wafer has been processed, the wafer is cut so as to separate the regions from one another to yield individual semiconductor chips.
Individual semiconductor chips can be mounted directly to a circuit board or other substrate by solder-bonding the contact pads of the chip directly to the circuit board, a process commonly referred to as “flip-chip” interconnection. However, such connections suffer from significant drawbacks including difficulties in testing chips before they are assembled to the circuit board and failure of the solder bonds due to stresses caused by thermal expansion and contraction of the components during manufacture and use. To avoid these difficulties, semiconductor chips have been mounted to circuit boards heretofore by wire-bonding. In wire-bonding, the chip is mounted face-up, with the contact bearing front face of the chip facing upwardly, away from the circuit board. Small wires are connected between individual contacts on the chip and the corresponding connections on the circuit board. As described, for example, in Matunami, U.S. Pat. No. 3,952,404 and Luro, U.S. Pat. No. 3,825,353, it has been proposed to provide leads on chips connected to the contact pads of the chips. The leads may be subsequently bonded to a circuit board or other substrate.
Other approaches to handling and mounting semiconductor chips include mounting the chips in packages having exposed terminals connected to the chip contacts and bonding the terminals of the packages to the circuit board. Numerous designs for chip packages have been proposed. Many of these involve packages structures which are considerably larger than the chips themselves. Moreover, some chip packages provide do not provide electrical connections with adequate reliability. As disclosed in the preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,518,964, the disclosures of which are hereby incorporated by reference herein, as well as other commonly assigned patents, a package semiconductor chip can be provided with terminals overlying a face of the chip and electrically connected to the contacts of the chip. Most commonly, the terminals are disposed on a supporting dielectric layer and a compliant layer such as a gel or elastomer may be disposed between the terminals and the chips as to mechanically de-couple the terminals from the chip and allow movement of the terminals with respect to the chip. Certain embodiments taught in these patents use flexible leads interconnecting the terminals and the chip. Although various fabrication methods may be employed to produce these assemblies, such assemblies most commonly are formed by fabricating the dielectric with the leads and terminals thereon and attaching the dielectric to the chips, either before or after severing the chips from the wafer. As described in co-pending, commonly assigned U.S. patent application Ser. No. 09/217,675, filed May 24, 1999, the disclosure of which is incorporated by reference herein, leads formed on the surface of a chip or wafer can be reliably interconnected with another element such as a circuit panel bearing leads.
The approaches disclosed in these commonly assigned patents and applications provide useful solutions to the problems of handling and mounting microelectronic elements such as semiconductor chips. Nonetheless, further development and additional solutions would be desirable.
SUMMARY OF THE INVENTION
One aspect of the present invention provides methods of processing a microelectronic element having a front face with a plurality of pads thereon. Methods according to this aspect of the invention desirably include providing a sacrificial layer overlying the front surface and forming leads on the sacrificial layer. Each lead typically has a pad end connected to a pad of the microelectronic element and a tip end. The sacrificial layer is then removed from beneath the leads. The sacrificial layer may be entirely removed from beneath the leads, so as to leave the lead tip ends independently movable with respect to the pads and the microelectronic element. That is, each lead can be flexed independently. Alternatively, the step of removing the sacrificial layer may be performed so to only partially remove the sacrificial layer and leave portions of the sacrificial layer beneath the tip ends of the leads releasably connecting the tip ends with the front face of the microelectronic element. As further discussed below, such releasably connected leads can be subjected to further processing which breaks the releasable connections, leaving the tips ends movable with respect to the pads and microelectronic elements. The step of forming the sacrificial layer may include forming apertures in the sacrificial layer in alignment with the pads on the microelectronic element, whereas the step of forming the leads may include the step of depositing one or more conductive materials onto the sacrificial layer so that the deposited conductive material contacts the pads at the apertures. The depositing step may be performed, for example, by plating or sputtering the conductive materials.
According to certain embodiments of the invention, the step of providing the sacrificial layer may be performed so as to form the sacrificial layer with regions of different thicknesses including thin regions and thick regions, and the leads may be formed so that they extend over both the thick regions and the thin regions. Thus, leads include sections disposed near to the front surface and sections disposed from the front surface. Most preferably, the sections remote from the front surface include the tip ends of the lead. The sacrificial layer with thin and thick regions may be formed by applying a first sub-layer on the front surface of the microelectronic element and applying a second sub-layer over the first sub-layer and selectively patterning the sub-layer, as by selectively applying the second sub-layer or, more preferably, by non-selectively applying the second sub-layer and selectively removing portions of the second sub-layer and leading other portions.
Yet another aspect of the present invention provides microelectronic elements including a body defining a front surface, the body having electrical contact pads exposed at the front surface. Flexible leads connected to the pads project from the pads, and at least some of the leads project over the front surface of the body. The leads are spaced apart from the front surface at least adjacent to tip ends thereof. The tip ends of the leads desirably are removable with respect to the body and independently movable with respect to one another. The body may be a semiconductor body such as a chip or a wafer incorporating a plurality of semiconductor chips. In this case, at least some of the leads associated with each chip desirably extend over the front face of such chip. Alternatively, the body ay be a connecting substrate such as a wafer probe card. As further discussed below, the leads may form the wafer-engaging probes of a wafer probe card.
These and other objects, features and advantages of the present invention will be more readily apparent from

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