Fabrication of conductive lines interconnecting conductive...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S319000, C257SE29300

Reexamination Certificate

active

11321982

ABSTRACT:
In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

REFERENCES:
patent: 5153143 (1992-10-01), Schlais et al.
patent: 5402371 (1995-03-01), Ono
patent: 5543339 (1996-08-01), Roth et al.
patent: 5723351 (1998-03-01), Bellezza
patent: 5856943 (1999-01-01), Jeng
patent: 5901084 (1999-05-01), Ohnakado
patent: 5929480 (1999-07-01), Hisamune
patent: 6057575 (2000-05-01), Jenq
patent: 6130129 (2000-10-01), Chen
patent: 6134144 (2000-10-01), Lin et al.
patent: 6171909 (2001-01-01), Ding et al.
patent: 6200856 (2001-03-01), Chen
patent: 6261856 (2001-07-01), Shinohara et al.
patent: 6266278 (2001-07-01), Harari et al.
patent: 6326661 (2001-12-01), Dormans et al.
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6365457 (2002-04-01), Choi
patent: 6414872 (2002-07-01), Bergemont et al.
patent: 6420231 (2002-07-01), Harari et al.
patent: 6437360 (2002-08-01), Cho et al.
patent: 6438036 (2002-08-01), Seki et al.
patent: 6448606 (2002-09-01), Yu et al.
patent: 6486023 (2002-11-01), Nagata
patent: 6512263 (2003-01-01), Yuan et al.
patent: 6518618 (2003-02-01), Fazio et al.
patent: 6541324 (2003-04-01), Wang
patent: 6541829 (2003-04-01), Nishinohara et al.
patent: 6667510 (2003-12-01), Wu
patent: 7049652 (2006-05-01), Mokhlesi et al.
patent: 2002/0064071 (2002-05-01), Takahashi et al.
patent: 2002/0197888 (2002-12-01), Huang et al.
patent: 2003/0218908 (2003-11-01), Park et al.
patent: 2004/0004863 (2004-01-01), Wang
patent: 0 938 098 (1999-08-01), None
Wu, A.T.; Chan T.Y.; Ko, P.K.; and Hu, C. “A Novel High-Speed, 5-Volt Programming EPROM Structure With Source-Side Injection,” 1986 IEEE, 584-587.
Mizutani, Yoshihisa; and Makita, Koji “A New EPROM Cell With A Sidewall Floating Gate Fro High-Density and High Performance Device,” 1985 IEEE, 635-638.
Ma, Y.; Pang, C.S.; Pathak, J.; Tsao, S.C.; Chang, C.F.; Yamauchi, Y.; Yoshimi, M. “A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell for 5V-Only Applications,” 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 49-50.
Mih, Rebecca et al. “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 120-121.
Ma, Yale et al., “A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single Vcc High Density Flash Memories,” 1994 IEEE, 3.5.1-3.5.4.
Spinelli, Alessandro S., “Quantum-Mechanical 2D Simulation of Surface-and Buried-Channel p-MOS,”2000 International Conference on Simulation of Semiconductor Processes and Devices: SISPAD 2000, Seattle, WA Sep. 6-8, 2000.
Kim, K.S. et al. “A Novel Dual String NOR (DuSnor) Memory Cell Technolgy Scalable to the 256 Mbit and 1 Gbit Flash Memories,” 1995 IEEE 11.1.1-11.1.4.
Bergemont, A. et al. “NOR Virtual Ground (NVG)- A New Scaling Concept for Very High Density FLAS EEPROM and its Implementation in a 0.5 um Process,” 1993 IEEE 2.2.1-2.2.4.
Van Duuren, Michiel et al., “Compact poly-CMP Embedded Flash Memory Cells For One or Two Bit Storage,” Philips Research Leuven, Kapeldreef 75, B3001 Leuven, Belgium, pp. 73-74.
U.S. Appl. No. 10/440,466, entitled “Fabrication Of Conductive Gates For Nonvolatile Memories from layers With Protruding Portions,” Filed on May 16, 2003.
U.S. Appl. No. 10/440,005, entitled “Fabrication of Dielectric On A Gate Surface To Insulate The Gate From Another Element Of An Integrated Circuit,” Filed on May 16, 2003.
U.S. Appl. No. 10/440,508, entitled “Fabrication Of Gate Dielectric In Nonvolatile Memories Having Select, Floating And Control Gates,” Filed on May 16, 2003.
U.S. Appl. No. 10/440,500, entitled “Integrated Circuits With Openings that Allow Electrical Contact To Conductive Features Having Self-Aligned Edges,” Filed on May 16, 2003.
U.S. Appl. No. 10/393,212, entitled “nonvolatile Memories And Methods Of Fabrication,” Filed on Mar. 19, 2003.
U.S. Appl. No. 10/411,813, entitled “Nonvolatile Memories With A Floating Gate Having An Upward Protrusion,” Filed on Apr. 10, 2003.
U.S. Appl. No. 10/393,202, entitled “Fabrication of Integrated Circuit Elements In Structures With Protruding Features,” Filed on Mar. 19, 2003.
U.S. Appl. No. 10/631,941, entitled “Nonvolatile Memory Cell With Multiple Floating Gates Formed After The Select Gate,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,155, entitled “Nonvolatile Memory Cells With Buried Channel Transistors,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,007, entitled “Arrays Of Nonvolatile Memory Cells Wherin Each Cell Has Two Conductive Floating Gates,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/631,452, entitled “Fabrication Of Dielectric For A Nonvolatile Memory Cell Having Multiple Floating Gates,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,154, entitled “Fabrication Of Gate Dielectric In Nonvolatile Memories In Which A Memory Cell Has Mutiple Floating Gates,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,186, entitled “Nonvolatile Memory Cell With Multiple Floating Gates Formed After The Select Gate And Having Upward Protrusions,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/631,552, entitled “Nonvolatile Memories And Methods Of Fabrication,” Filed on Jul. 30, 2003.
Shirota, Riichiro “A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend,” Feb. 2000, Nonvolatile Memory Workshop in Monterey, California, pp. 22-31.
U.S. Appl. No. 10/797,972, entitled “Fabrication Of Conductive Lines Interconnecting First Conductive Gates In Nonvolatile Memories Having Second Conductive Gates Provided By Conductive Gate Lines, Wherein The Adjacent Conductive Gate Lines For The Adjacent Columns Are Spaced From Each Other, And Non-Volatile Memory Structures,” Filed on Mar. 10, 2004.

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