Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-03-15
2001-12-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06326291
ABSTRACT:
TECHNICAL FIELD
This invention relates to MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and more particularly to fabrication of a wide metal silicide on a narrow polysilicon gate structure of a MOSFET for a gate with low series resistance for MOSFETs with scaled down dimensions.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a cross sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
includes a drain region
102
, a source region
104
, and a channel region
106
fabricated on an insulating layer
107
disposed over a semiconductor substrate
108
for SOI (silicon-on-insulator) technology, as known to one of ordinary skill in the art of electronics. A gate dielectric
110
is disposed over the channel region
106
of the MOSFET
100
. The MOSFET
100
also includes a gate comprised of a polysilicon gate structure
112
disposed over the gate dielectric
110
. Spacer structures
113
typically formed of an insulating material surround the gate dielectric
110
and the polysilicon gate structure
112
, as known to one of ordinary skill in the art of electronics. Isolation dielectric structures
120
electrically isolate the MOSFET
100
from other devices fabricated on the insulating layer
107
.
For making contact to the drain region
102
, the source region
104
, and the polysilicon gate structure
112
of the gate, a metal silicide is formed on the drain region
102
, the source region
104
, and the polysilicon gate structure
112
of the gate. A drain silicide
114
is formed on the drain region
102
, a source silicide
116
is formed on the source region
104
, and a gate silicide
118
is formed on the polysilicon gate structure
112
of the gate of the MOSFET
100
.
For efficiency in fabrication, the drain silicide
114
, the source silicide
116
, and the gate silicide
118
are typically fabricated simultaneously in the prior art. During the fabrication of the silicides, the drain region
102
, the source region
104
, and the polysilicon gate structure
112
are exposed, and metal is deposited on those regions. Then, a silicidation anneal is performed, and the drain silicide
114
, the source silicide
116
, and the gate silicide
118
form from a reaction of the deposited metal with silicon during the silicidation anneal. Thus, in the prior art, the drain silicide
114
, the source silicide
116
, and the gate silicide
118
have substantially the same thickness and is comprised of substantially the same metal silicide material.
However, as structures of the MOSFET are modified with advancement in technology, it may be desired that the thickness of the drain silicide
114
and the source silicide
116
be different from the thickness of the gate silicide
118
. In addition, it may be desired that the metal silicide material for the drain silicide
114
and the source silicide
116
be different from the metal silicide material of the gate silicide
118
.
For example, a long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is to enhance the speed performance of the integrated circuit. Thus, the MOSFET
100
is fabricated with SOI (silicon-on-insulator) technology whereby the drain region
102
, the source region
104
, and the channel region
106
are fabricated on the insulating layer
107
to eliminate junction capacitance, as known to one of ordinary skill in the art of electronics. Because the drain region
102
and the source region
104
are fabricated directly on the insulating layer
107
, the depth of the drain region
102
and the source region
104
may be limited. In that case, the thickness of the drain silicide
114
and the source silicide
116
in turn are limited. On the other hand, a large thickness of the gate silicide
118
is desired for minimizing the resistance at the gate of the MOSFET and in turn for maximizing the speed performance of the MOSFET.
In addition, another long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, as the dimensions of the MOSFET
100
are scaled down, a smaller thickness is desired for the drain silicide
114
and the source silicide
116
to minimize small channel effects of the MOSFET, as known to one of ordinary skill in the art. On the other hand, a large thickness of the gate silicide
118
is desired for minimizing the resistance at the gate of the MOSFET and in turn for maximizing the speed performance of the MOSFET.
Some metal silicides, such as nickel silicide (NiSi
2
), are more amenable for forming a thin metal silicide. Thus, it may be desired that the drain silicide
114
and the source silicide
116
be comprised of nickel silicide (NiSi
2
). Other metal silicides, such as cobalt silicide (CoSi
2
) or titanium silicide (TiSi
2
), are more amenable for forming a thick metal silicide. Thus, it may be desired that the gate silicide
118
be comprised of cobalt silicide (CoSi
2
) or titanium silicide (TiSi
2
) while the drain silicide
114
and the source silicide
116
may be comprised of nickel silicide (NiSi
2
) such that the gate silicide
118
is comprised of a different metal silicide material from that of the drain silicide
114
and the source silicide
116
.
Furthermore, with scaling down of the dimensions of the polysilicon gate structure
112
of the MOSFET, the volume of the gate silicide
118
is also scaled down resulting in higher series resistance at the gate of the MOSFET
100
. Such higher series resistance degrades the speed performance of the MOSFET.
Thus, a gate silicide is desired to have a larger thickness than that of the drain silicide and the source silicide, and to be comprised of a metal silicide material that may be different from that for the drain silicide and the source silicide. In addition, a gate silicide is desired to have a larger width than that of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a separate step for fabrication of the gate silicide from the step for fabrication of the drain silicide and the source silicide such that the gate silicide may have a different thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide. In addition, the gate silicide is formed from the top and the sidewalls of a top portion of a polysilicon gate structure that is exposed such that the gate silicide has a larger width that the width of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
In a general aspect of the present invention, in a method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric over the channel region. A drain silicide is formed in the drain region, and a source silicide is formed in the source region. The drain silicide and the source silicide have a first silicide thickness. A first dielectric layer is conformally deposited over the drain region, the source region, and the gate. The first dielectric layer is polished down until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level.
A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon gate structure are exposed. The capping layer on the polysilicon gate structure of the gate is etched away such that the top of the polysilicon gate structure is ex
Advanced Micro Devices , Inc.
Choi Monica H.
Huang Quoc
Nelms David
LandOfFree
Fabrication of a wide metal silicide on a narrow polysilicon... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication of a wide metal silicide on a narrow polysilicon..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of a wide metal silicide on a narrow polysilicon... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2584607